Module tim1

Source
Expand description

TIM1 address block description

Re-exports§

pub use ccr as ccr6;
pub use CCR as CCR6;

Modules§

af1
TIM1 alternate function option register 1
af2
TIM1 Alternate function register 2
arr
TIM1 auto-reload register
bdtr
TIM1 break and dead-time register
ccer
TIM1 capture/compare enable register
ccmr1_input
TIM1 capture/compare mode register 1
ccmr1_output
TIM1 capture/compare mode register 1
ccmr2_input
TIM1 capture/compare mode register 2
ccmr2_output
TIM1 capture/compare mode register 2
ccmr3_output
TIM1 capture/compare mode register 3
ccr
capture/compare register
ccr5
capture/compare register
cnt
TIM1 counter
cr1
TIM1 control register 1
cr2
TIM1 control register 2
dcr
TIM1 DMA control register
dier
TIM1 DMA/interrupt enable register
dmar
TIM1 DMA address for full transfer
egr
TIM1 event generation register
psc
TIM1 prescaler
rcr
TIM1 repetition counter register
smcr
TIM1 slave mode control register
sr
TIM1 status register
tisel
TIM1 timer input selection register

Structs§

RegisterBlock
Register block

Type Aliases§

AF1
AF1 (rw) register accessor: TIM1 alternate function option register 1
AF2
AF2 (rw) register accessor: TIM1 Alternate function register 2
ARR
ARR (rw) register accessor: TIM1 auto-reload register
BDTR
BDTR (rw) register accessor: TIM1 break and dead-time register
CCER
CCER (rw) register accessor: TIM1 capture/compare enable register
CCMR1_INPUT
CCMR1_Input (rw) register accessor: TIM1 capture/compare mode register 1
CCMR1_OUTPUT
CCMR1_Output (rw) register accessor: TIM1 capture/compare mode register 1
CCMR2_INPUT
CCMR2_Input (rw) register accessor: TIM1 capture/compare mode register 2
CCMR2_OUTPUT
CCMR2_Output (rw) register accessor: TIM1 capture/compare mode register 2
CCMR3_OUTPUT
CCMR3_Output (rw) register accessor: TIM1 capture/compare mode register 3
CCR
CCR (rw) register accessor: capture/compare register
CCR5
CCR5 (rw) register accessor: capture/compare register
CNT
CNT (rw) register accessor: TIM1 counter
CR1
CR1 (rw) register accessor: TIM1 control register 1
CR2
CR2 (rw) register accessor: TIM1 control register 2
DCR
DCR (rw) register accessor: TIM1 DMA control register
DIER
DIER (rw) register accessor: TIM1 DMA/interrupt enable register
DMAR
DMAR (rw) register accessor: TIM1 DMA address for full transfer
EGR
EGR (w) register accessor: TIM1 event generation register
PSC
PSC (rw) register accessor: TIM1 prescaler
RCR
RCR (rw) register accessor: TIM1 repetition counter register
SMCR
SMCR (rw) register accessor: TIM1 slave mode control register
SR
SR (rw) register accessor: TIM1 status register
TISEL
TISEL (rw) register accessor: TIM1 timer input selection register