Module cr1 

Power control register 1

Structs

CR1rs

Power control register 1

Type Aliases

DBP_R

Field DBP reader - Disable backup domain write protection In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers.

DBP_W

Field DBP writer - Disable backup domain write protection In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers.

FPD_STOP_R

Field FPD_STOP reader - FPD_STOP

FPD_STOP_W

Field FPD_STOP writer - FPD_STOP

LPMS_R

Field LPMS reader - Low-power mode selection These bits select the low-power mode entered when CPU enters the deepsleep mode. 1xx: Shutdown mode Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3.

LPMS_W

Field LPMS writer - Low-power mode selection These bits select the low-power mode entered when CPU enters the deepsleep mode. 1xx: Shutdown mode Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3.

LPR_R

Field LPR reader - Low-power run When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR).

LPR_W

Field LPR writer - Low-power run When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR).

R

Register CR1 reader

VOS_R

Field VOS reader - Voltage scaling range selection

VOS_W

Field VOS writer - Voltage scaling range selection

W

Register CR1 writer