Module lpuart1 

Universal synchronous asynchronous receiver transmitter

Modules

brr

Baud rate register

cr1

Control register 1

cr2

Control register 2

cr3

Control register 3

icr

Interrupt flag clear register

isr

Interrupt & status register

presc

Prescaler register

rdr

Receive data register

rqr

Request register

tdr

Transmit data register

Structs

RegisterBlock

Register block

Type Aliases

BRR

BRR (rw) register accessor: Baud rate register

CR1

CR1 (rw) register accessor: Control register 1

CR2

CR2 (rw) register accessor: Control register 2

CR3

CR3 (rw) register accessor: Control register 3

ICR

ICR (w) register accessor: Interrupt flag clear register

ISR

ISR (r) register accessor: Interrupt & status register

PRESC

PRESC (rw) register accessor: Prescaler register

RDR

RDR (r) register accessor: Receive data register

RQR

RQR (w) register accessor: Request register

TDR

TDR (rw) register accessor: Transmit data register