Module hrtim_timd

Module hrtim_timd 

Source
Expand description

High Resolution Timer: TIMD

Modules§

cpt1cr
Timerx Capture 2 Control Register
cr
Timerx Control Register
rst1r
Timerx Output1 Reset Register
rstr
TimerA Reset Register
set1r
Timerx Output1 Set Register

Structs§

RegisterBlock
Register block

Type Aliases§

CHPR
CHPR (rw) register accessor: Timerx Chopper Register
CMP1CR
CMP1CR (rw) register accessor: Timerx Compare 1 Compound Register
CMP1R
CMP1R (rw) register accessor: Master Timer Compare 1 Register
CMP2R
CMP1R (rw) register accessor: Master Timer Compare 1 Register
CMP3R
CMP1R (rw) register accessor: Master Timer Compare 1 Register
CMP4R
CMP1R (rw) register accessor: Master Timer Compare 1 Register
CNTR
CNTR (rw) register accessor: Master Timer Counter Register
CPT1CR
CPT1CR (rw) register accessor: Timerx Capture 2 Control Register
CPT1R
CPT1R (r) register accessor: Timerx Capture 1 Register
CPT2CR
CPT1CR (rw) register accessor: Timerx Capture 2 Control Register
CPT2R
CPT1R (r) register accessor: Timerx Capture 1 Register
CR
CR (rw) register accessor: Timerx Control Register
CR2
CR2 (rw) register accessor: HRTIM Timerx Control Register 2
DIER
DIER (rw) register accessor: TIMxDIER
DTR
DTR (rw) register accessor: Timerx Deadtime Register
EEFR1
EEFR1 (rw) register accessor: Timerx External Event Filtering Register 1
EEFR2
EEFR2 (rw) register accessor: Timerx External Event Filtering Register 2
EEFR3
EEFR3 (rw) register accessor: HRTIM Timerx External Event Filtering Register 3
FLTR
FLTR (rw) register accessor: Timerx Fault Register
ICR
ICR (w) register accessor: Timerx Interrupt Clear Register
ISR
ISR (r) register accessor: Timerx Interrupt Status Register
OUTR
OUTR (rw) register accessor: Timerx Output Register
PERR
PERR (rw) register accessor: Master Timer Period Register
REPR
REPR (rw) register accessor: Master Timer Repetition Register
RST1R
RST1R (rw) register accessor: Timerx Output1 Reset Register
RST2R
RST1R (rw) register accessor: Timerx Output1 Reset Register
RSTR
RSTR (rw) register accessor: TimerA Reset Register
SET1R
SET1R (rw) register accessor: Timerx Output1 Set Register
SET2R
SET1R (rw) register accessor: Timerx Output1 Set Register