Module ckdiv 

FDCAN CFG clock divider register

Structs

CKDIVrs

FDCAN CFG clock divider register

Type Aliases

PDIV_R

Field PDIV reader - input clock divider The APB clock could be divided prior to be used by the CAN sub system. The rate must be computed using the divider output clock. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

PDIV_W

Field PDIV writer - input clock divider The APB clock could be divided prior to be used by the CAN sub system. The rate must be computed using the divider output clock. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

R

Register CKDIV reader

W

Register CKDIV writer