Enum CLK48SEL

#[repr(u8)]
pub enum CLK48SEL {
    Hsi48 = 0,
    Pllq = 2,
}

48 MHz clock source selection These bits are set and cleared by software to select the 48 MHz clock source used by USB device FS and RNG.

Value on reset: 0

Variants

Hsi48 = 0

0: HSI48 clock selected as 48MHz clock

Pllq = 2

2: PLL ‘Q’ (PLL48M1CLK) clock selected as 48MHz clock

Trait Implementations

impl Clone for CLK48SEL

fn clone(&self) -> CLK48SEL

Returns a duplicate of the value.

const fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for CLK48SEL

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl FieldSpec for CLK48SEL

type Ux = u8

Raw field type (u8, u16, u32, …).

impl PartialEq for CLK48SEL

fn eq(&self, other: &CLK48SEL) -> bool

Tests for self and other values to be equal, and is used by ==.

const fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for CLK48SEL

impl Eq for CLK48SEL

impl IsEnum for CLK48SEL

impl StructuralPartialEq for CLK48SEL