Struct stm32_hal2::clocks::Clocks
source · pub struct Clocks {Show 24 fields
pub input_src: InputSrc,
pub pll_src: PllSrc,
pub pll1: PllCfg,
pub pll2: PllCfg,
pub pll3: PllCfg,
pub d1_core_prescaler: HclkPrescaler,
pub hclk_prescaler: HclkPrescaler,
pub d1_prescaler: ApbPrescaler,
pub d2_prescaler1: ApbPrescaler,
pub d2_prescaler2: ApbPrescaler,
pub d3_prescaler: ApbPrescaler,
pub hse_bypass: bool,
pub usb_src: UsbSrc,
pub security_system: bool,
pub hsi48_on: bool,
pub stop_wuck: StopWuck,
pub vos_range: VosRange,
pub sai1_src: SaiSrc,
pub sai4a_src: SaiSrc,
pub sai4b_src: SaiSrc,
pub spi123_src: Spi123Src,
pub spi45_src: Spi45Src,
pub dfsdm1_src: DfsdmSrc,
pub can_src: CanSrc,
}
Expand description
Settings used to configure clocks. Create this struct by using its Default::default()
implementation, then modify as required, referencing your RM’s clock tree,
or Stm32Cube IDE’s interactive clock manager. Apply settings by running .setup()
.
Fields§
§input_src: InputSrc
The main input source
pll_src: PllSrc
The source driving all PLLs.
pll1: PllCfg
Enable and speed status for PLL1. Note that input_src
controls if PLL1 is enabled, not
pll1.enabled()
.
pll2: PllCfg
Enable and speed status for PLL2
pll3: PllCfg
Enable and speed status for PLL3
d1_core_prescaler: HclkPrescaler
The prescaler between sysclk and hclk
hclk_prescaler: HclkPrescaler
The value to divide SYSCLK by, to get systick and peripheral clocks. Also known as AHB divider
d1_prescaler: ApbPrescaler
APB3 peripheral clocks
d2_prescaler1: ApbPrescaler
APB1 peripheral clocks
d2_prescaler2: ApbPrescaler
APB2 peripheral clocks
d3_prescaler: ApbPrescaler
APB4 peripheral clocks
hse_bypass: bool
Bypass the HSE output, for use with oscillators that don’t need it. Saves power, and frees up the pin for use as GPIO.
usb_src: UsbSrc
USBOTG kernel clock selection. Defaults to HSI48.
security_system: bool
§hsi48_on: bool
§stop_wuck: StopWuck
§vos_range: VosRange
§sai1_src: SaiSrc
SAI1 and DFSDM1 kernel Aclk clock source selection
sai4a_src: SaiSrc
§sai4b_src: SaiSrc
§spi123_src: Spi123Src
§spi45_src: Spi45Src
§dfsdm1_src: DfsdmSrc
DFSDM1 kernel clock source selection
can_src: CanSrc
FDCAN kernel clock selection. Defaults to PLL1Q.
Implementations§
source§impl Clocks
impl Clocks
sourcepub fn setup(&self) -> Result<(), RccError>
pub fn setup(&self) -> Result<(), RccError>
Setup common and return Ok if the config is valid. Abort the setup if speeds
are invalid.
Use the STM32CubeIDE Clock Configuration tab to identify valid configs.
Use the default()
implementation as a safe baseline.
This method also configures the PWR VOS setting, and can be used to enable VOS boost,
if vos_range
is set to VosRange::VOS0
.
sourcepub fn reselect_input(&self) -> Result<(), RccError>
pub fn reselect_input(&self) -> Result<(), RccError>
Re-select input source; used on Stop and Standby modes, where the system reverts to HSI after wake.
sourcepub fn pll_input_speed(&self, pll_src: PllSrc, pll_num: u8) -> u32
pub fn pll_input_speed(&self, pll_src: PllSrc, pll_num: u8) -> u32
Calculate the input speed to the PLL. This must be between 1 and 16 Mhz. Called refx_ck
in the RM.
sourcepub fn vco_output_freq(&self, pll_src: PllSrc, pll_num: u8) -> u32
pub fn vco_output_freq(&self, pll_src: PllSrc, pll_num: u8) -> u32
Calculate VCO output frequency: = Fref1_ck x DIVN1
sourcepub fn pll_is_enabled(&self) -> bool
pub fn pll_is_enabled(&self) -> bool
Check if the PLL is enabled. This is useful if checking whether to re-enable the PLL after exiting Stop or Standby modes, eg so you don’t re-enable if it was already re-enabled in a different context. eg:
if !clock_cfg.pll_is_enabled() {
clock_cfg.reselect_input();
}
sourcepub fn sysclk(&self) -> u32
pub fn sysclk(&self) -> u32
Calculate the sysclock frequency, in hz. Note that for dual core variants, this is for CPU1.
CPU2 syclock is equal to the HCLK, so use the hclk()
method.
sourcepub fn systick(&self) -> u32
pub fn systick(&self) -> u32
Get the systick speed. Note that for dual core variants, this is for CPU1.
CPU2 systick is equal to the HCLK (possibly divided by 8), so use the hclk()
method.
pub fn apb1(&self) -> u32
sourcepub fn apb1_timer(&self) -> u32
pub fn apb1_timer(&self) -> u32
Get the frequency used by APB1 timers, in hz
pub fn apb2(&self) -> u32
sourcepub fn apb2_timer(&self) -> u32
pub fn apb2_timer(&self) -> u32
Get the frequency used by APB2 timers, in hz
sourcepub fn sai1_speed(&self) -> u32
pub fn sai1_speed(&self) -> u32
Get the SAI1 audio clock frequency, in hz
pub fn validate_speeds(&self) -> Result<(), RccError>
source§impl Clocks
impl Clocks
sourcepub fn full_speed() -> Self
pub fn full_speed() -> Self
Full speed of 480Mhz, with VC0 range 0. Correspondingly higher periph clock speeds as well. (520Mhz core speed on H723-35) Note that special consideration needs to be taken when using low power modes (ie anything with wfe or wfi) in this mode; may need to manually disable and re-enable it.
Note that this overwrites some fields of the pll1 config.
Trait Implementations§
source§impl Default for Clocks
impl Default for Clocks
source§fn default() -> Self
fn default() -> Self
This default configures clocks with the HSI, and a 400Mhz sysclock speed. (280Mhz sysclock on variants that only go that high). Note that H723-745 still use this default speed due to needing VOS0 for higher. Peripheral and timer clocks are set to 100Mhz or 200Mhz, depending on their limits. HSE output is not bypassed.