Struct Clocks

pub struct Clocks {
    pub input_src: InputSrc,
    pub pll: PllCfg,
    pub hclk_prescaler: HclkPrescaler,
    pub apb1_prescaler: ApbPrescaler,
    pub apb2_prescaler: ApbPrescaler,
    pub clk48_src: Clk48Src,
    pub lpuart_src: LpUartSrc,
    pub hse_bypass: bool,
    pub security_system: bool,
    pub hsi48_on: bool,
    pub boost_mode: bool,
    pub can_src: CanSrc,
}

Settings used to configure clocks. Create this struct by using its Default::default() implementation, then modify as required, referencing your RM’s clock tree, or Stm32Cube IDE’s interactive clock manager. Apply settings by running .setup().

Fields

input_src: InputSrc

The input source for the system and peripheral clocks. Eg HSE, HSI, PLL etc

pll: PllCfg

Enable and speed status for the main PLL

hclk_prescaler: HclkPrescaler

The value to divide SYSCLK by, to get systick and peripheral clocks. Also known as AHB divider

apb1_prescaler: ApbPrescaler

The divider of HCLK to get the APB1 peripheral clock

apb2_prescaler: ApbPrescaler

The divider of HCLK to get the APB2 peripheral clock

clk48_src: Clk48Src

The input source for the 48Mhz clock used by USB.

lpuart_src: LpUartSrc

hse_bypass: bool

Bypass the HSE output, for use with oscillators that don’t need it. Saves power, and frees up the pin for use as GPIO.

security_system: bool

hsi48_on: bool

Enable the HSI48. For L4, this is only applicable for some devices.

boost_mode: bool

Range 1 boost mode: Used to increase regulator voltage to 1.28v, for when system clock frequency is up to 170Mhz. Defaults to true.

can_src: CanSrc

FDCAN kernel clock selection. Defaults to APB1.

Implementations

impl Clocks

pub fn setup(&self) -> Result<(), RccError>

Setup common and return Ok if the config is valid. Abort the setup if speeds are invalid. Use the STM32CubeIDE Clock Configuration tab to help identify valid configs. Use the default() implementation as a safe baseline.

pub fn reselect_input(&self) -> Result<(), RccError>

Re-select input source; used after Stop and Standby modes, where the system reverts to MSI or HSI after wake.

pub fn sysclk(&self) -> u32

Get the sysclock frequency, in hz.

pub fn pll_is_enabled(&self) -> bool

Check if the PLL is enabled. This is useful if checking whether to re-enable the PLL after exiting Stop or Standby modes, eg so you don’t re-enable if it was already re-enabled in a different context. eg:

if !clock_cfg.pll_is_enabled() {
    clock_cfg.reselect_input();
}

pub fn hclk(&self) -> u32

Get the HCLK frequency, in hz

pub fn systick(&self) -> u32

Get the systick frequency, in hz

pub fn usb(&self) -> u32

pub fn apb1(&self) -> u32

Get the APB1 peripheral clock frequency frequency, in hz

pub fn apb1_timer(&self) -> u32

Get the frequency used by APB1 timers, in hz

pub fn apb2(&self) -> u32

Get the APB2 peipheral clock frequency, in hz.

pub fn apb2_timer(&self) -> u32

pub fn validate_speeds(&self) -> Result<(), RccError>

Trait Implementations

impl Default for Clocks

fn default() -> Self

This default configures clocks with a HSI, with system and peripheral clocks at full rated speed. All peripheral. Speeds -> L4: 80Mhz. L5: 110Mhz. G0: 64Mhz. G4: 170Mhz. WB: 64Mhz.