Module dma 

Support for the Direct Memory Access (DMA) peripheral. This module handles initialization, and transfer configuration for DMA. The dma::cfg_channel method is called by modules that use DMA.

Structs

ChannelCfg

This struct is used to pass common (non-peripheral and non-use-specific) data when configuring a channel.

Dma

Represents a Direct Memory Access (DMA) peripheral.

Dma1Ch1

Experimental/WIP channel-based DMA struct.

Dma1Ch2

Experimental/WIP channel-based DMA struct.

Dma1Ch3

Experimental/WIP channel-based DMA struct.

Dma1Ch4

Experimental/WIP channel-based DMA struct.

Dma1Ch5

Experimental/WIP channel-based DMA struct.

Dma1Ch6

Experimental/WIP channel-based DMA struct.

Dma1Ch7

Experimental/WIP channel-based DMA struct.

Dma1Ch8

Experimental/WIP channel-based DMA struct.

Dma2Ch1

Experimental/WIP channel-based DMA struct.

Dma2Ch2

Experimental/WIP channel-based DMA struct.

Dma2Ch3

Experimental/WIP channel-based DMA struct.

Dma2Ch4

Experimental/WIP channel-based DMA struct.

Dma2Ch5

Experimental/WIP channel-based DMA struct.

Dma2Ch6

Experimental/WIP channel-based DMA struct.

Dma2Ch7

Experimental/WIP channel-based DMA struct.

Dma2Ch8

Experimental/WIP channel-based DMA struct.

Enums

Circular

Set in ccr(). Can only be set when channel is disabled.

DataSize

Peripheral and memory increment mode. (CCR PSIZE and MSIZE bits) Can only be set when channel is disabled.

Direction

Set in ccr(). Can only be set when channel is disabled.

DmaChannel

Represents a DMA channel to select, eg when configuring for use with a peripheral. u8 representation is used to index registers on H7 PAC (And hopefully on future PACs if they adopt H7’s approach)

DmaError

Errors that can occur when performing DMA.

DmaInput

A list of DMA input sources. The integer values represent their DMAMUX register value, on MCUs that use this. G4 RM, Table 91: DMAMUX: Assignment of multiplexer inputs to resources.

DmaInterrupt

Interrupt type. Set in CCR using TEIE, HTIE, and TCIE bits. Can only be set when channel is disabled.

DmaPeriph

IncrMode

Peripheral and memory increment mode. (CCR PINC and MINC bits) Can only be set when channel is disabled.

Priority

L4 RM, 11.4.3, “DMA arbitration”: The priorities are managed in two stages: • software: priority of each channel is configured in the DMA_CCRx register, to one of the four different levels: – very high – high – medium – low • hardware: if two requests have the same software priority level, the channel with the lowest index gets priority. For example, channel 2 gets priority over channel 4. Only write to this when the channel is disabled.

Functions

cfg_channel

Configure a DMA channel. See L4 RM 0394, section 11.4.4. Sets the Transfer Complete interrupt. This is the function called by various module read_dma and write_dma functions.

clear_interrupt

Clear an interrupt flag.

disable_interrupt

Disable a specific type of interrupt.

enable_interrupt

Enable a specific type of interrupt.

enable_mux1

Enable the DMA mux RCC clock. Applicable to some variants, but no others. (H7 and G0 don’t use it, for example)

mux

Configure a specific DMA channel to work with a specific peripheral.

stop

Stop a DMA transfer, if in progress.