Type Alias stm32_hal2::pac::fmc::sdbank::sdtr::TRC_W

pub type TRC_W<'a, const O: u8> = FieldWriterRaw<'a, u32, SDTR_SPEC, u8, u8, Unsafe, 4, O>;

Field TRC writer - Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. …. Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are dont care.

Aliased Type

struct TRC_W<'a, const O: u8> { /* private fields */ }