Module stm32_hal2::pac::fmc::sdbank::sdtr

This register contains the timing parameters of each SDRAM bank

Structs

• R
  Register SDTR reader
• SDTR_SPEC
  This register contains the timing parameters of each SDRAM bank
• W
  Register SDTR writer

Type Aliases

• TMRD_R
  Field TMRD reader - Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. ….
• TMRD_W
  Field TMRD writer - Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. ….
• TRAS_R
  Field TRAS reader - Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. ….
• TRAS_W
  Field TRAS writer - Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. ….
• TRCD_R
  Field TRCD reader - Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. ….
• TRCD_W
  Field TRCD writer - Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. ….
• TRC_R
  Field TRC reader - Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. …. Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are dont care.
• TRC_W
  Field TRC writer - Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. …. Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are dont care.
• TRP_R
  Field TRP reader - Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. …. Note: The corresponding bits in the FMC_SDTR2 register are dont care.
• TRP_W
  Field TRP writer - Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. …. Note: The corresponding bits in the FMC_SDTR2 register are dont care.
• TWR_R
  Field TWR reader - Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. …. Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device.
• TWR_W
  Field TWR writer - Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. …. Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device.
• TXSR_R
  Field TXSR reader - Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. …. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device.
• TXSR_W
  Field TXSR writer - Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. …. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device.