Module stm32_hal2::pac::ethernet_mac::macl3l4c1r

L3 and L4 control 1 register

Structs

• MACL3L4C1R_SPEC
  L3 and L4 control 1 register
• R
  Register MACL3L4C1R reader
• W
  Register MACL3L4C1R writer

Type Aliases

• L3DAIM1_R
  Field L3DAIM1 reader - Layer 3 IP DA Inverse Match Enable
• L3DAIM1_W
  Field L3DAIM1 writer - Layer 3 IP DA Inverse Match Enable
• L3DAM1_R
  Field L3DAM1 reader - Layer 3 IP DA Match Enable
• L3DAM1_W
  Field L3DAM1 writer - Layer 3 IP DA Match Enable
• L3HDBM1_R
  Field L3HDBM1 reader - Layer 3 IP DA Higher Bits Match
• L3HDBM1_W
  Field L3HDBM1 writer - Layer 3 IP DA Higher Bits Match
• L3HSBM1_R
  Field L3HSBM1 reader - Layer 3 IP SA Higher Bits Match
• L3HSBM1_W
  Field L3HSBM1 writer - Layer 3 IP SA Higher Bits Match
• L3PEN1_R
  Field L3PEN1 reader - Layer 3 Protocol Enable
• L3PEN1_W
  Field L3PEN1 writer - Layer 3 Protocol Enable
• L3SAIM1_R
  Field L3SAIM1 reader - Layer 3 IP SA Inverse Match Enable
• L3SAIM1_W
  Field L3SAIM1 writer - Layer 3 IP SA Inverse Match Enable
• L3SAM1_R
  Field L3SAM1 reader - Layer 3 IP SA Match Enable
• L3SAM1_W
  Field L3SAM1 writer - Layer 3 IP SA Match Enable
• L4DPIM1_R
  Field L4DPIM1 reader - Layer 4 Destination Port Inverse Match Enable
• L4DPIM1_W
  Field L4DPIM1 writer - Layer 4 Destination Port Inverse Match Enable
• L4DPM1_R
  Field L4DPM1 reader - Layer 4 Destination Port Match Enable
• L4DPM1_W
  Field L4DPM1 writer - Layer 4 Destination Port Match Enable
• L4PEN1_R
  Field L4PEN1 reader - Layer 4 Protocol Enable
• L4PEN1_W
  Field L4PEN1 writer - Layer 4 Protocol Enable
• L4SPIM1_R
  Field L4SPIM1 reader - Layer 4 Source Port Inverse Match Enable
• L4SPIM1_W
  Field L4SPIM1 writer - Layer 4 Source Port Inverse Match Enable
• L4SPM1_R
  Field L4SPM1 reader - Layer 4 Source Port Match Enable
• L4SPM1_W
  Field L4SPM1 writer - Layer 4 Source Port Match Enable