Enum stm32_hal2::pac::dmamux1::ccr::DMAREQ_ID_A
source · #[repr(u8)]pub enum DMAREQ_ID_A {
Show 115 variants
None = 0,
Dmamux1ReqGen0 = 1,
Dmamux1ReqGen1 = 2,
Dmamux1ReqGen2 = 3,
Dmamux1ReqGen3 = 4,
Dmamux1ReqGen4 = 5,
Dmamux1ReqGen5 = 6,
Dmamux1ReqGen6 = 7,
Dmamux1ReqGen7 = 8,
Adc1Dma = 9,
Adc2Dma = 10,
Tim1Ch1 = 11,
Tim1Ch2 = 12,
Tim1Ch3 = 13,
Tim1Ch4 = 14,
Tim1Up = 15,
Tim1Trig = 16,
Tim1Com = 17,
Tim2Ch1 = 18,
Tim2Ch2 = 19,
Tim2Ch3 = 20,
Tim2Ch4 = 21,
Tim2Up = 22,
Tim3Ch1 = 23,
Tim3Ch2 = 24,
Tim3Ch3 = 25,
Tim3Ch4 = 26,
Tim3Up = 27,
Tim3Trig = 28,
Tim4Ch1 = 29,
Tim4Ch2 = 30,
Tim4Ch3 = 31,
Tim4Up = 32,
I2c1RxDma = 33,
I2c1TxDma = 34,
I2c2RxDma = 35,
I2c2TxDma = 36,
Spi1RxDma = 37,
Spi1TxDma = 38,
Spi2RxDma = 39,
Spi2TxDma = 40,
Usart1RxDma = 41,
Usart1TxDma = 42,
Usart2RxDma = 43,
Usart2TxDma = 44,
Usart3RxDma = 45,
Usart3TxDma = 46,
Tim8Ch1 = 47,
Tim8Ch2 = 48,
Tim8Ch3 = 49,
Tim8Ch4 = 50,
Tim8Up = 51,
Tim8Trig = 52,
Tim8Com = 53,
Tim5Ch1 = 55,
Tim5Ch2 = 56,
Tim5Ch3 = 57,
Tim5Ch4 = 58,
Tim5Up = 59,
Tim5Trig = 60,
Spi3RxDma = 61,
Spi3TxDma = 62,
Uart4RxDma = 63,
Uart4TxDma = 64,
Uart5RxDma = 65,
Uart5TxDma = 66,
DacCh1Dma = 67,
DacCh2Dma = 68,
Tim6Up = 69,
Tim7Up = 70,
Usart6RxDma = 71,
Usart6TxDma = 72,
I2c3RxDma = 73,
I2c3TxDma = 74,
DcmiDma = 75,
CrypInDma = 76,
CrypOutDma = 77,
HashInDma = 78,
Uart7RxDma = 79,
Uart7TxDma = 80,
Uart8RxDma = 81,
Uart8TxDma = 82,
Spi4RxDma = 83,
Spi4TxDma = 84,
Spi5RxDma = 85,
Spi5TxDma = 86,
Sai1aDma = 87,
Sai1bDma = 88,
Sai2aDma = 89,
Sai2bDma = 90,
SwpmiRxDma = 91,
SwpmiTxDma = 92,
SpdifrxDatDma = 93,
SpdifrxCtrlDma = 94,
HrReq1 = 95,
HrReq2 = 96,
HrReq3 = 97,
HrReq4 = 98,
HrReq5 = 99,
HrReq6 = 100,
Dfsdm1Dma0 = 101,
Dfsdm1Dma1 = 102,
Dfsdm1Dma2 = 103,
Dfsdm1Dma3 = 104,
Tim15Ch1 = 105,
Tim15Up = 106,
Tim15Trig = 107,
Tim15Com = 108,
Tim16Ch1 = 109,
Tim16Up = 110,
Tim17Ch1 = 111,
Tim17Up = 112,
Sai3ADma = 113,
Sai3BDma = 114,
Adc3Dma = 115,
}Expand description
Input DMA request line selected
Value on reset: 0
Variants§
None = 0
0: No signal selected as request input
Dmamux1ReqGen0 = 1
1: Signal dmamux1_req_gen0 selected as request input
Dmamux1ReqGen1 = 2
2: Signal dmamux1_req_gen1 selected as request input
Dmamux1ReqGen2 = 3
3: Signal dmamux1_req_gen2 selected as request input
Dmamux1ReqGen3 = 4
4: Signal dmamux1_req_gen3 selected as request input
Dmamux1ReqGen4 = 5
5: Signal dmamux1_req_gen4 selected as request input
Dmamux1ReqGen5 = 6
6: Signal dmamux1_req_gen5 selected as request input
Dmamux1ReqGen6 = 7
7: Signal dmamux1_req_gen6 selected as request input
Dmamux1ReqGen7 = 8
8: Signal dmamux1_req_gen7 selected as request input
Adc1Dma = 9
9: Signal adc1_dma selected as request input
Adc2Dma = 10
10: Signal adc2_dma selected as request input
Tim1Ch1 = 11
11: Signal tim1_ch1 selected as request input
Tim1Ch2 = 12
12: Signal tim1_ch2 selected as request input
Tim1Ch3 = 13
13: Signal tim1_ch3 selected as request input
Tim1Ch4 = 14
14: Signal tim1_ch4 selected as request input
Tim1Up = 15
15: Signal tim1_up selected as request input
Tim1Trig = 16
16: Signal tim1_trig selected as request input
Tim1Com = 17
17: Signal tim1_com selected as request input
Tim2Ch1 = 18
18: Signal tim2_ch1 selected as request input
Tim2Ch2 = 19
19: Signal tim2_ch2 selected as request input
Tim2Ch3 = 20
20: Signal tim2_ch3 selected as request input
Tim2Ch4 = 21
21: Signal tim2_ch4 selected as request input
Tim2Up = 22
22: Signal tim2_up selected as request input
Tim3Ch1 = 23
23: Signal tim3_ch1 selected as request input
Tim3Ch2 = 24
24: Signal tim3_ch2 selected as request input
Tim3Ch3 = 25
25: Signal tim3_ch3 selected as request input
Tim3Ch4 = 26
26: Signal tim3_ch4 selected as request input
Tim3Up = 27
27: Signal tim3_up selected as request input
Tim3Trig = 28
28: Signal tim3_trig selected as request input
Tim4Ch1 = 29
29: Signal tim4_ch1 selected as request input
Tim4Ch2 = 30
30: Signal tim4_ch2 selected as request input
Tim4Ch3 = 31
31: Signal tim4_ch3 selected as request input
Tim4Up = 32
32: Signal tim4_up selected as request input
I2c1RxDma = 33
33: Signal i2c1_rx_dma selected as request input
I2c1TxDma = 34
34: Signal i2c1_tx_dma selected as request input
I2c2RxDma = 35
35: Signal i2c2_rx_dma selected as request input
I2c2TxDma = 36
36: Signal i2c2_tx_dma selected as request input
Spi1RxDma = 37
37: Signal spi1_rx_dma selected as request input
Spi1TxDma = 38
38: Signal spi1_tx_dma selected as request input
Spi2RxDma = 39
39: Signal spi2_rx_dma selected as request input
Spi2TxDma = 40
40: Signal spi2_tx_dma selected as request input
Usart1RxDma = 41
41: Signal usart1_rx_dma selected as request input
Usart1TxDma = 42
42: Signal usart1_tx_dma selected as request input
Usart2RxDma = 43
43: Signal usart2_rx_dma selected as request input
Usart2TxDma = 44
44: Signal usart2_tx_dma selected as request input
Usart3RxDma = 45
45: Signal usart3_rx_dma selected as request input
Usart3TxDma = 46
46: Signal usart3_tx_dma selected as request input
Tim8Ch1 = 47
47: Signal tim8_ch1 selected as request input
Tim8Ch2 = 48
48: Signal tim8_ch2 selected as request input
Tim8Ch3 = 49
49: Signal tim8_ch3 selected as request input
Tim8Ch4 = 50
50: Signal tim8_ch4 selected as request input
Tim8Up = 51
51: Signal tim8_up selected as request input
Tim8Trig = 52
52: Signal tim8_trig selected as request input
Tim8Com = 53
53: Signal tim8_com selected as request input
Tim5Ch1 = 55
55: Signal tim5_ch1 selected as request input
Tim5Ch2 = 56
56: Signal tim5_ch2 selected as request input
Tim5Ch3 = 57
57: Signal tim5_ch3 selected as request input
Tim5Ch4 = 58
58: Signal tim5_ch4 selected as request input
Tim5Up = 59
59: Signal tim5_up selected as request input
Tim5Trig = 60
60: Signal tim5_trig selected as request input
Spi3RxDma = 61
61: Signal spi3_rx_dma selected as request input
Spi3TxDma = 62
62: Signal spi3_tx_dma selected as request input
Uart4RxDma = 63
63: Signal uart4_rx_dma selected as request input
Uart4TxDma = 64
64: Signal uart4_tx_dma selected as request input
Uart5RxDma = 65
65: Signal uart5_rx_dma selected as request input
Uart5TxDma = 66
66: Signal uart5_tx_dma selected as request input
DacCh1Dma = 67
67: Signal dac_ch1_dma selected as request input
DacCh2Dma = 68
68: Signal dac_ch2_dma selected as request input
Tim6Up = 69
69: Signal tim6_up selected as request input
Tim7Up = 70
70: Signal tim7_up selected as request input
Usart6RxDma = 71
71: Signal usart6_rx_dma selected as request input
Usart6TxDma = 72
72: Signal usart6_tx_dma selected as request input
I2c3RxDma = 73
73: Signal i2c3_rx_dma selected as request input
I2c3TxDma = 74
74: Signal i2c3_tx_dma selected as request input
DcmiDma = 75
75: Signal dcmi_dma selected as request input
CrypInDma = 76
76: Signal cryp_in_dma selected as request input
CrypOutDma = 77
77: Signal cryp_out_dma selected as request input
HashInDma = 78
78: Signal hash_in_dma selected as request input
Uart7RxDma = 79
79: Signal uart7_rx_dma selected as request input
Uart7TxDma = 80
80: Signal uart7_tx_dma selected as request input
Uart8RxDma = 81
81: Signal uart8_rx_dma selected as request input
Uart8TxDma = 82
82: Signal uart8_tx_dma selected as request input
Spi4RxDma = 83
83: Signal spi4_rx_dma selected as request input
Spi4TxDma = 84
84: Signal spi4_tx_dma selected as request input
Spi5RxDma = 85
85: Signal spi5_rx_dma selected as request input
Spi5TxDma = 86
86: Signal spi5_tx_dma selected as request input
Sai1aDma = 87
87: Signal sai1a_dma selected as request input
Sai1bDma = 88
88: Signal sai1b_dma selected as request input
Sai2aDma = 89
89: Signal sai2a_dma selected as request input
Sai2bDma = 90
90: Signal sai2b_dma selected as request input
SwpmiRxDma = 91
91: Signal swpmi_rx_dma selected as request input
SwpmiTxDma = 92
92: Signal swpmi_tx_dma selected as request input
SpdifrxDatDma = 93
93: Signal spdifrx_dat_dma selected as request input
SpdifrxCtrlDma = 94
94: Signal spdifrx_ctrl_dma selected as request input
HrReq1 = 95
95: Signal hr_req(1) selected as request input
HrReq2 = 96
96: Signal hr_req(2) selected as request input
HrReq3 = 97
97: Signal hr_req(3) selected as request input
HrReq4 = 98
98: Signal hr_req(4) selected as request input
HrReq5 = 99
99: Signal hr_req(5) selected as request input
HrReq6 = 100
100: Signal hr_req(6) selected as request input
Dfsdm1Dma0 = 101
101: Signal dfsdm1_dma0 selected as request input
Dfsdm1Dma1 = 102
102: Signal dfsdm1_dma1 selected as request input
Dfsdm1Dma2 = 103
103: Signal dfsdm1_dma2 selected as request input
Dfsdm1Dma3 = 104
104: Signal dfsdm1_dma3 selected as request input
Tim15Ch1 = 105
105: Signal tim15_ch1 selected as request input
Tim15Up = 106
106: Signal tim15_up selected as request input
Tim15Trig = 107
107: Signal tim15_trig selected as request input
Tim15Com = 108
108: Signal tim15_com selected as request input
Tim16Ch1 = 109
109: Signal tim16_ch1 selected as request input
Tim16Up = 110
110: Signal tim16_up selected as request input
Tim17Ch1 = 111
111: Signal tim17_ch1 selected as request input
Tim17Up = 112
112: Signal tim17_up selected as request input
Sai3ADma = 113
113: Signal sai3_a_dma selected as request input
Sai3BDma = 114
114: Signal sai3_b_dma selected as request input
Adc3Dma = 115
115: Signal adc3_dma selected as request input
Trait Implementations§
source§impl Clone for DMAREQ_ID_A
impl Clone for DMAREQ_ID_A
source§fn clone(&self) -> DMAREQ_ID_A
fn clone(&self) -> DMAREQ_ID_A
1.0.0 · source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read moresource§impl Debug for DMAREQ_ID_A
impl Debug for DMAREQ_ID_A
source§impl PartialEq for DMAREQ_ID_A
impl PartialEq for DMAREQ_ID_A
source§fn eq(&self, other: &DMAREQ_ID_A) -> bool
fn eq(&self, other: &DMAREQ_ID_A) -> bool
self and other values to be equal, and is used
by ==.