pub struct W(/* private fields */);
Expand description
Register CR1
writer
Implementations§
source§impl W
impl W
sourcepub fn awfsel(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 30>
pub fn awfsel(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 30>
Bit 30 - Analog watchdog fast mode select
sourcepub fn fast(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 29>
pub fn fast(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 29>
Bit 29 - Fast conversion mode selection for regular conversions
sourcepub fn rch(
&mut self
) -> FieldWriterRaw<'_, u32, CR1_SPEC, u8, u8, Unsafe, 3, 24>
pub fn rch( &mut self ) -> FieldWriterRaw<'_, u32, CR1_SPEC, u8, u8, Unsafe, 3, 24>
Bits 24:26 - Regular channel selection
sourcepub fn rdmaen(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 21>
pub fn rdmaen(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 21>
Bit 21 - DMA channel enabled to read data for the regular conversion
sourcepub fn rsync(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 19>
pub fn rsync(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 19>
Bit 19 - Launch regular conversion synchronously with DFSDM0
sourcepub fn rcont(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 18>
pub fn rcont(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 18>
Bit 18 - Continuous mode selection for regular conversions
sourcepub fn rswstart(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 17>
pub fn rswstart(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 17>
Bit 17 - Software start of a conversion on the regular channel
sourcepub fn jexten(
&mut self
) -> FieldWriterRaw<'_, u32, CR1_SPEC, u8, u8, Unsafe, 2, 13>
pub fn jexten( &mut self ) -> FieldWriterRaw<'_, u32, CR1_SPEC, u8, u8, Unsafe, 2, 13>
Bits 13:14 - Trigger enable and trigger edge selection for injected conversions
sourcepub fn jextsel(
&mut self
) -> FieldWriterRaw<'_, u32, CR1_SPEC, u8, u8, Unsafe, 3, 8>
pub fn jextsel( &mut self ) -> FieldWriterRaw<'_, u32, CR1_SPEC, u8, u8, Unsafe, 3, 8>
Bits 8:10 - Trigger signal selection for launching injected conversions
sourcepub fn jdmaen(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 5>
pub fn jdmaen(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 5>
Bit 5 - DMA channel enabled to read data for the injected channel group
sourcepub fn jscan(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 4>
pub fn jscan(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 4>
Bit 4 - Scanning conversion mode for injected conversions
sourcepub fn jsync(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 3>
pub fn jsync(&mut self) -> BitWriterRaw<'_, u32, CR1_SPEC, bool, BitM, 3>
Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
Methods from Deref<Target = W<CR1_SPEC>>§
sourcepub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>
Writes raw bits to the register.