Struct stm32_hal2::adc::Adc

pub struct Adc<R> {
    pub regs: R,
    pub cfg: AdcConfig,
    pub vdda_calibrated: f32,
    /* private fields */
}

Represents an Analog to Digital Converter (ADC) peripheral.

Fields

regs: R

ADC Register

cfg: AdcConfig

vdda_calibrated: f32

This field is managed internally, and is set up on init.

Implementations

impl Adc<ADC1>

pub fn new_adc1( regs: ADC1, device: AdcDevice, cfg: AdcConfig, ahb_freq: u32 ) -> Self

Initialize an ADC peripheral, including configuration register writes, enabling and resetting its RCC peripheral clock, and calibrtation.

If used with ADC1, this also performs VDDA measurement, used for converting raw output to voltage. If using an ADC other than ADC1, this measurement is skipped, and 3.3V is assumed. In this case, it’s recommended to setup ADC1, read it’s VDDA value (vdda_calibrated field), and update the ADC in question with it.

pub fn set_sequence_len(&mut self, len: u8)

Set the ADC conversion sequence length, between 1 and 16.

pub fn set_align(&self, align: Align)

Set the alignment mode.

pub fn enable(&mut self)

Enable the ADC. ADEN=1 enables the ADC. The flag ADRDY will be set once the ADC is ready for operation.

pub fn disable(&mut self)

Disable the ADC. ADDIS=1 disables the ADC. ADEN and ADDIS are then automatically cleared by hardware as soon as the analog ADC is effectively disabled

pub fn stop_conversions(&mut self)

If any conversions are in progress, stop them. This is a step listed in the RMs for disable, and calibration procedures. See L4 RM: 16.4.17. When the ADSTP bit is set by software, any ongoing regular conversion is aborted with partial result discarded (ADC_DR register is not updated with the current conversion). When the JADSTP bit is set by software, any ongoing injected conversion is aborted with partial result discarded (ADC_JDRy register is not updated with the current conversion). The scan sequence is also aborted and reset (meaning that relaunching the ADC would restart a new sequence).

pub fn is_enabled(&self) -> bool

Check if the ADC is enabled.

pub fn is_advregen_enabled(&self) -> bool

Check if the ADC voltage regulator is enabled.

pub fn advregen_enable(&mut self, ahb_freq: u32)

Enable the ADC voltage regulator, and exit deep sleep mode (some MCUs)

pub fn advregen_disable(&mut self)

Disable power, eg to save power in low power modes. Inferred from RM, we should run this before entering STOP mode, in conjunction with with disabling the ADC.

pub fn calibrate(&mut self, input_type: InputType, ahb_freq: u32)

Calibrate. See L4 RM, 16.5.8, or F404 RM, section 15.3.8. Stores calibration values, which can be re-inserted later, eg after entering ADC deep sleep mode, or MCU STANDBY or VBAT.

pub fn inject_calibration(&mut self)

Insert a previously-saved calibration value into the ADC. Se L4 RM, 16.4.8.

pub fn set_input_type(&mut self, channel: u8, input_type: InputType)

Select single-ended, or differential conversions for a given channel.

pub fn set_sequence(&mut self, chan: u8, position: u8)

Select a sequence to sample, by inputting a single channel and position.

pub fn set_sample_time(&mut self, chan: u8, smp: SampleTime)

Select the sample time for a given channel.

pub fn reading_to_voltage(&self, reading: u16) -> f32

Convert a raw measurement into a voltage in Volts, using the calibrated VDDA. See RM0394, section 16.4.34

pub fn start_conversion(&mut self, sequence: &[u8])

Start a conversion: Either a single measurement, or continuous conversions. Blocks until the conversion is complete. See L4 RM 16.4.15 for details.

pub fn read_result(&mut self) -> u16

Read data from a conversion. In OneShot mode, this will generally be run right after start_conversion.

pub fn read(&mut self, channel: u8) -> u16

Take a single reading; return a raw integer value.

pub fn read_voltage(&mut self, channel: u8) -> f32

Take a single reading; return a voltage.

pub fn set_trigger(&mut self, trigger: Trigger, edge: TriggerEdge)

Select and activate a trigger. See G4 RM, section 21.4.18: Conversion on external trigger and trigger polarit

pub unsafe fn read_dma( &mut self, buf: &mut [u16], adc_channels: &[u8], dma_channel: DmaChannel, channel_cfg: ChannelCfg, dma_periph: DmaPeriph )

Take a reading, using DMA. Sets conversion sequence; no need to set it directly. Note that the channel argument is unused on F3 and L4, since it is hard-coded, and can’t be configured using the DMAMUX peripheral. (dma::mux() fn).

pub fn enable_interrupt(&mut self, interrupt: AdcInterrupt)

Enable a specific type of ADC interrupt.

pub fn clear_interrupt(&mut self, interrupt: AdcInterrupt)

Clear an interrupt flag of the specified type. Consider running this in the corresponding ISR.

pub fn read_status(&self) -> u32

Print the (raw) contents of the status register.

impl Adc<ADC2>

pub fn new_adc2( regs: ADC2, device: AdcDevice, cfg: AdcConfig, ahb_freq: u32 ) -> Self

Initialize an ADC peripheral, including configuration register writes, enabling and resetting its RCC peripheral clock, and calibrtation.

If used with ADC1, this also performs VDDA measurement, used for converting raw output to voltage. If using an ADC other than ADC1, this measurement is skipped, and 3.3V is assumed. In this case, it’s recommended to setup ADC1, read it’s VDDA value (vdda_calibrated field), and update the ADC in question with it.

pub fn set_sequence_len(&mut self, len: u8)

Set the ADC conversion sequence length, between 1 and 16.

pub fn set_align(&self, align: Align)

Set the alignment mode.

pub fn enable(&mut self)

Enable the ADC. ADEN=1 enables the ADC. The flag ADRDY will be set once the ADC is ready for operation.

pub fn disable(&mut self)

Disable the ADC. ADDIS=1 disables the ADC. ADEN and ADDIS are then automatically cleared by hardware as soon as the analog ADC is effectively disabled

pub fn stop_conversions(&mut self)

If any conversions are in progress, stop them. This is a step listed in the RMs for disable, and calibration procedures. See L4 RM: 16.4.17. When the ADSTP bit is set by software, any ongoing regular conversion is aborted with partial result discarded (ADC_DR register is not updated with the current conversion). When the JADSTP bit is set by software, any ongoing injected conversion is aborted with partial result discarded (ADC_JDRy register is not updated with the current conversion). The scan sequence is also aborted and reset (meaning that relaunching the ADC would restart a new sequence).

pub fn is_enabled(&self) -> bool

Check if the ADC is enabled.

pub fn is_advregen_enabled(&self) -> bool

Check if the ADC voltage regulator is enabled.

pub fn advregen_enable(&mut self, ahb_freq: u32)

Enable the ADC voltage regulator, and exit deep sleep mode (some MCUs)

pub fn advregen_disable(&mut self)

Disable power, eg to save power in low power modes. Inferred from RM, we should run this before entering STOP mode, in conjunction with with disabling the ADC.

pub fn calibrate(&mut self, input_type: InputType, ahb_freq: u32)

Calibrate. See L4 RM, 16.5.8, or F404 RM, section 15.3.8. Stores calibration values, which can be re-inserted later, eg after entering ADC deep sleep mode, or MCU STANDBY or VBAT.

pub fn inject_calibration(&mut self)

Insert a previously-saved calibration value into the ADC. Se L4 RM, 16.4.8.

pub fn set_input_type(&mut self, channel: u8, input_type: InputType)

Select single-ended, or differential conversions for a given channel.

pub fn set_sequence(&mut self, chan: u8, position: u8)

Select a sequence to sample, by inputting a single channel and position.

pub fn set_sample_time(&mut self, chan: u8, smp: SampleTime)

Select the sample time for a given channel.

pub fn reading_to_voltage(&self, reading: u16) -> f32

Convert a raw measurement into a voltage in Volts, using the calibrated VDDA. See RM0394, section 16.4.34

pub fn start_conversion(&mut self, sequence: &[u8])

Start a conversion: Either a single measurement, or continuous conversions. Blocks until the conversion is complete. See L4 RM 16.4.15 for details.

pub fn read_result(&mut self) -> u16

Read data from a conversion. In OneShot mode, this will generally be run right after start_conversion.

pub fn read(&mut self, channel: u8) -> u16

Take a single reading; return a raw integer value.

pub fn read_voltage(&mut self, channel: u8) -> f32

Take a single reading; return a voltage.

pub fn set_trigger(&mut self, trigger: Trigger, edge: TriggerEdge)

Select and activate a trigger. See G4 RM, section 21.4.18: Conversion on external trigger and trigger polarit

pub unsafe fn read_dma( &mut self, buf: &mut [u16], adc_channels: &[u8], dma_channel: DmaChannel, channel_cfg: ChannelCfg, dma_periph: DmaPeriph )

Take a reading, using DMA. Sets conversion sequence; no need to set it directly. Note that the channel argument is unused on F3 and L4, since it is hard-coded, and can’t be configured using the DMAMUX peripheral. (dma::mux() fn).

pub fn enable_interrupt(&mut self, interrupt: AdcInterrupt)

Enable a specific type of ADC interrupt.

pub fn clear_interrupt(&mut self, interrupt: AdcInterrupt)

Clear an interrupt flag of the specified type. Consider running this in the corresponding ISR.

pub fn read_status(&self) -> u32

Print the (raw) contents of the status register.

impl Adc<ADC3>

pub fn new_adc3( regs: ADC3, device: AdcDevice, cfg: AdcConfig, ahb_freq: u32 ) -> Self

Initialize an ADC peripheral, including configuration register writes, enabling and resetting its RCC peripheral clock, and calibrtation.

If used with ADC1, this also performs VDDA measurement, used for converting raw output to voltage. If using an ADC other than ADC1, this measurement is skipped, and 3.3V is assumed. In this case, it’s recommended to setup ADC1, read it’s VDDA value (vdda_calibrated field), and update the ADC in question with it.

pub fn set_sequence_len(&mut self, len: u8)

Set the ADC conversion sequence length, between 1 and 16.

pub fn set_align(&self, align: Align)

Set the alignment mode.

pub fn enable(&mut self)

Enable the ADC. ADEN=1 enables the ADC. The flag ADRDY will be set once the ADC is ready for operation.

pub fn disable(&mut self)

Disable the ADC. ADDIS=1 disables the ADC. ADEN and ADDIS are then automatically cleared by hardware as soon as the analog ADC is effectively disabled

pub fn stop_conversions(&mut self)

If any conversions are in progress, stop them. This is a step listed in the RMs for disable, and calibration procedures. See L4 RM: 16.4.17. When the ADSTP bit is set by software, any ongoing regular conversion is aborted with partial result discarded (ADC_DR register is not updated with the current conversion). When the JADSTP bit is set by software, any ongoing injected conversion is aborted with partial result discarded (ADC_JDRy register is not updated with the current conversion). The scan sequence is also aborted and reset (meaning that relaunching the ADC would restart a new sequence).

pub fn is_enabled(&self) -> bool

Check if the ADC is enabled.

pub fn is_advregen_enabled(&self) -> bool

Check if the ADC voltage regulator is enabled.

pub fn advregen_enable(&mut self, ahb_freq: u32)

Enable the ADC voltage regulator, and exit deep sleep mode (some MCUs)

pub fn advregen_disable(&mut self)

Disable power, eg to save power in low power modes. Inferred from RM, we should run this before entering STOP mode, in conjunction with with disabling the ADC.

pub fn calibrate(&mut self, input_type: InputType, ahb_freq: u32)

Calibrate. See L4 RM, 16.5.8, or F404 RM, section 15.3.8. Stores calibration values, which can be re-inserted later, eg after entering ADC deep sleep mode, or MCU STANDBY or VBAT.

pub fn inject_calibration(&mut self)

Insert a previously-saved calibration value into the ADC. Se L4 RM, 16.4.8.

pub fn set_input_type(&mut self, channel: u8, input_type: InputType)

Select single-ended, or differential conversions for a given channel.

pub fn set_sequence(&mut self, chan: u8, position: u8)

Select a sequence to sample, by inputting a single channel and position.

pub fn set_sample_time(&mut self, chan: u8, smp: SampleTime)

Select the sample time for a given channel.

pub fn reading_to_voltage(&self, reading: u16) -> f32

Convert a raw measurement into a voltage in Volts, using the calibrated VDDA. See RM0394, section 16.4.34

pub fn start_conversion(&mut self, sequence: &[u8])

Start a conversion: Either a single measurement, or continuous conversions. Blocks until the conversion is complete. See L4 RM 16.4.15 for details.

pub fn read_result(&mut self) -> u16

Read data from a conversion. In OneShot mode, this will generally be run right after start_conversion.

pub fn read(&mut self, channel: u8) -> u16

Take a single reading; return a raw integer value.

pub fn read_voltage(&mut self, channel: u8) -> f32

Take a single reading; return a voltage.

pub fn set_trigger(&mut self, trigger: Trigger, edge: TriggerEdge)

Select and activate a trigger. See G4 RM, section 21.4.18: Conversion on external trigger and trigger polarit

pub unsafe fn read_dma( &mut self, buf: &mut [u16], adc_channels: &[u8], dma_channel: DmaChannel, channel_cfg: ChannelCfg, dma_periph: DmaPeriph )

Take a reading, using DMA. Sets conversion sequence; no need to set it directly. Note that the channel argument is unused on F3 and L4, since it is hard-coded, and can’t be configured using the DMAMUX peripheral. (dma::mux() fn).

pub fn enable_interrupt(&mut self, interrupt: AdcInterrupt)

Enable a specific type of ADC interrupt.

pub fn clear_interrupt(&mut self, interrupt: AdcInterrupt)

Clear an interrupt flag of the specified type. Consider running this in the corresponding ISR.

pub fn read_status(&self) -> u32

Print the (raw) contents of the status register.