pub type CLKDIV_W<'a, const O: u8> = FieldWriterRaw<'a, u32, CLKCR_SPEC, u16, u16, Unsafe, 10, O>;Expand description
Field CLKDIV writer - Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc..