Struct stm32_hal2::pac::octospi1::RegisterBlock
source · [−]#[repr(C)]pub struct RegisterBlock {Show 27 fields
pub cr: Reg<CR_SPEC>,
pub dcr1: Reg<DCR1_SPEC>,
pub dcr2: Reg<DCR2_SPEC>,
pub dcr3: Reg<DCR3_SPEC>,
pub dcr4: Reg<DCR4_SPEC>,
pub sr: Reg<SR_SPEC>,
pub fcr: Reg<FCR_SPEC>,
pub dlr: Reg<DLR_SPEC>,
pub ar: Reg<AR_SPEC>,
pub dr: Reg<DR_SPEC>,
pub psmkr: Reg<PSMKR_SPEC>,
pub psmar: Reg<PSMAR_SPEC>,
pub pir: Reg<PIR_SPEC>,
pub ccr: Reg<CCR_SPEC>,
pub tcr: Reg<TCR_SPEC>,
pub ir: Reg<IR_SPEC>,
pub abr: Reg<ABR_SPEC>,
pub lptr: Reg<LPTR_SPEC>,
pub wpccr: Reg<WPCCR_SPEC>,
pub wptcr: Reg<WPTCR_SPEC>,
pub wpir: Reg<WPIR_SPEC>,
pub wpabr: Reg<WPABR_SPEC>,
pub wccr: Reg<WCCR_SPEC>,
pub wtcr: Reg<WTCR_SPEC>,
pub wir: Reg<WIR_SPEC>,
pub wabr: Reg<WABR_SPEC>,
pub hlcr: Reg<HLCR_SPEC>,
/* private fields */
}Expand description
Register block
Fields
cr: Reg<CR_SPEC>0x00 - control register
dcr1: Reg<DCR1_SPEC>0x08 - device configuration register
dcr2: Reg<DCR2_SPEC>0x0c - device configuration register 2
dcr3: Reg<DCR3_SPEC>0x10 - device configuration register 3
dcr4: Reg<DCR4_SPEC>0x14 - DCR4
sr: Reg<SR_SPEC>0x20 - status register
fcr: Reg<FCR_SPEC>0x24 - flag clear register
dlr: Reg<DLR_SPEC>0x40 - data length register
ar: Reg<AR_SPEC>0x48 - address register
dr: Reg<DR_SPEC>0x50 - data register
psmkr: Reg<PSMKR_SPEC>0x80 - polling status mask register
psmar: Reg<PSMAR_SPEC>0x88 - polling status match register
pir: Reg<PIR_SPEC>0x90 - OCTOSPI polling interval register
ccr: Reg<CCR_SPEC>0x100 - polling interval register
tcr: Reg<TCR_SPEC>0x108 - communication configuration register
ir: Reg<IR_SPEC>0x110 - timing configuration register
abr: Reg<ABR_SPEC>0x120 - instruction register
lptr: Reg<LPTR_SPEC>0x130 - alternate bytes register
wpccr: Reg<WPCCR_SPEC>0x140 - low-power timeout register
wptcr: Reg<WPTCR_SPEC>0x148 - wrap timing configuration register
wpir: Reg<WPIR_SPEC>0x150 - wrap instruction register
wpabr: Reg<WPABR_SPEC>0x160 - wrap alternate bytes register
wccr: Reg<WCCR_SPEC>0x180 - write communication configuration register
wtcr: Reg<WTCR_SPEC>0x188 - write timing configuration register
wir: Reg<WIR_SPEC>0x190 - instruction register
wabr: Reg<WABR_SPEC>0x1a0 - write alternate bytes register
hlcr: Reg<HLCR_SPEC>0x200 - HyperBusTM latency configuration register