Struct stm32_hal2::pac::fmc::sr::SR_SPEC

pub struct SR_SPEC;

This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see sr module

Trait Implementations

impl Readable for SR_SPEC

read() method returns sr::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for SR_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for SR_SPEC

reset() method sets SR to value 0x40

fn reset_value() -> <SR_SPEC as RegisterSpec>::Ux

Reset value of the register.

impl Writable for SR_SPEC

write(|w| ..) method takes sr::W writer structure

type Writer = W

Writer type argument to write, et al.