Struct stm32_hal2::pac::fmc::sdbank::sdtr::W

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pub struct W(_);

Expand description

Register SDTR writer

Implementations

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impl W

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pub fn tmrd(
&mut self
) -> FieldWriterRaw<'_, u32, SDTR_SPEC, u8, u8, Unsafe, 4, 0>

Bits 0:3 - Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. ….

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pub fn txsr(
&mut self
) -> FieldWriterRaw<'_, u32, SDTR_SPEC, u8, u8, Unsafe, 4, 4>

Bits 4:7 - Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. …. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device.

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pub fn tras(
&mut self
) -> FieldWriterRaw<'_, u32, SDTR_SPEC, u8, u8, Unsafe, 4, 8>

Bits 8:11 - Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. ….

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pub fn trc(
&mut self
) -> FieldWriterRaw<'_, u32, SDTR_SPEC, u8, u8, Unsafe, 4, 12>

Bits 12:15 - Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. …. Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are dont care.

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pub fn twr(
&mut self
) -> FieldWriterRaw<'_, u32, SDTR_SPEC, u8, u8, Unsafe, 4, 16>

Bits 16:19 - Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. …. Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed to 0x1. If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device.

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pub fn trp(
&mut self
) -> FieldWriterRaw<'_, u32, SDTR_SPEC, u8, u8, Unsafe, 4, 20>

Bits 20:23 - Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. …. Note: The corresponding bits in the FMC_SDTR2 register are dont care.

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pub fn trcd(
&mut self
) -> FieldWriterRaw<'_, u32, SDTR_SPEC, u8, u8, Unsafe, 4, 24>

Bits 24:27 - Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. ….

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