Struct stm32_hal2::pac::fmc::eccr::ECCR_SPEC

pub struct ECCR_SPEC;

This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.

This register you can read. See API.

For information about available fields see eccr module

Trait Implementations

impl Readable for ECCR_SPEC

read() method returns eccr::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for ECCR_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for ECCR_SPEC

reset() method sets ECCR to value 0

fn reset_value() -> <ECCR_SPEC as RegisterSpec>::Ux

Reset value of the register.