Struct stm32_hal2::pac::fdcan1::RegisterBlock
source · [−]#[repr(C)]pub struct RegisterBlock {Show 64 fields
pub crel: Reg<CREL_SPEC>,
pub endn: Reg<ENDN_SPEC>,
pub dbtp: Reg<DBTP_SPEC>,
pub test: Reg<TEST_SPEC>,
pub rwd: Reg<RWD_SPEC>,
pub cccr: Reg<CCCR_SPEC>,
pub nbtp: Reg<NBTP_SPEC>,
pub tscc: Reg<TSCC_SPEC>,
pub tscv: Reg<TSCV_SPEC>,
pub tocc: Reg<TOCC_SPEC>,
pub tocv: Reg<TOCV_SPEC>,
pub ecr: Reg<ECR_SPEC>,
pub psr: Reg<PSR_SPEC>,
pub tdcr: Reg<TDCR_SPEC>,
pub ir: Reg<IR_SPEC>,
pub ie: Reg<IE_SPEC>,
pub ils: Reg<ILS_SPEC>,
pub ile: Reg<ILE_SPEC>,
pub gfc: Reg<GFC_SPEC>,
pub sidfc: Reg<SIDFC_SPEC>,
pub xidfc: Reg<XIDFC_SPEC>,
pub xidam: Reg<XIDAM_SPEC>,
pub hpms: Reg<HPMS_SPEC>,
pub ndat1: Reg<NDAT1_SPEC>,
pub ndat2: Reg<NDAT2_SPEC>,
pub rxf0c: Reg<RXF0C_SPEC>,
pub rxf0s: Reg<RXF0S_SPEC>,
pub rxf0a: Reg<RXF0A_SPEC>,
pub rxbc: Reg<RXBC_SPEC>,
pub rxf1c: Reg<RXF1C_SPEC>,
pub rxf1s: Reg<RXF1S_SPEC>,
pub rxf1a: Reg<RXF1A_SPEC>,
pub rxesc: Reg<RXESC_SPEC>,
pub txbc: Reg<TXBC_SPEC>,
pub txfqs: Reg<TXFQS_SPEC>,
pub txesc: Reg<TXESC_SPEC>,
pub txbrp: Reg<TXBRP_SPEC>,
pub txbar: Reg<TXBAR_SPEC>,
pub txbcr: Reg<TXBCR_SPEC>,
pub txbto: Reg<TXBTO_SPEC>,
pub txbcf: Reg<TXBCF_SPEC>,
pub txbtie: Reg<TXBTIE_SPEC>,
pub txbcie: Reg<TXBCIE_SPEC>,
pub txefc: Reg<TXEFC_SPEC>,
pub txefs: Reg<TXEFS_SPEC>,
pub txefa: Reg<TXEFA_SPEC>,
pub tttmc: Reg<TTTMC_SPEC>,
pub ttrmc: Reg<TTRMC_SPEC>,
pub ttocf: Reg<TTOCF_SPEC>,
pub ttmlm: Reg<TTMLM_SPEC>,
pub turcf: Reg<TURCF_SPEC>,
pub ttocn: Reg<TTOCN_SPEC>,
pub ttgtp: Reg<TTGTP_SPEC>,
pub tttmk: Reg<TTTMK_SPEC>,
pub ttir: Reg<TTIR_SPEC>,
pub ttie: Reg<TTIE_SPEC>,
pub ttils: Reg<TTILS_SPEC>,
pub ttost: Reg<TTOST_SPEC>,
pub turna: Reg<TURNA_SPEC>,
pub ttlgt: Reg<TTLGT_SPEC>,
pub ttctc: Reg<TTCTC_SPEC>,
pub ttcpt: Reg<TTCPT_SPEC>,
pub ttcsm: Reg<TTCSM_SPEC>,
pub ttts: Reg<TTTS_SPEC>,
/* private fields */
}
Expand description
Register block
Fields
crel: Reg<CREL_SPEC>
0x00 - FDCAN Core Release Register
endn: Reg<ENDN_SPEC>
0x04 - FDCAN Core Release Register
dbtp: Reg<DBTP_SPEC>
0x0c - FDCAN Data Bit Timing and Prescaler Register
test: Reg<TEST_SPEC>
0x10 - FDCAN Test Register
rwd: Reg<RWD_SPEC>
0x14 - FDCAN RAM Watchdog Register
cccr: Reg<CCCR_SPEC>
0x18 - FDCAN CC Control Register
nbtp: Reg<NBTP_SPEC>
0x1c - FDCAN Nominal Bit Timing and Prescaler Register
tscc: Reg<TSCC_SPEC>
0x20 - FDCAN Timestamp Counter Configuration Register
tscv: Reg<TSCV_SPEC>
0x24 - FDCAN Timestamp Counter Value Register
tocc: Reg<TOCC_SPEC>
0x28 - FDCAN Timeout Counter Configuration Register
tocv: Reg<TOCV_SPEC>
0x2c - FDCAN Timeout Counter Value Register
ecr: Reg<ECR_SPEC>
0x40 - FDCAN Error Counter Register
psr: Reg<PSR_SPEC>
0x44 - FDCAN Protocol Status Register
tdcr: Reg<TDCR_SPEC>
0x48 - FDCAN Transmitter Delay Compensation Register
ir: Reg<IR_SPEC>
0x50 - FDCAN Interrupt Register
ie: Reg<IE_SPEC>
0x54 - FDCAN Interrupt Enable Register
ils: Reg<ILS_SPEC>
0x58 - FDCAN Interrupt Line Select Register
ile: Reg<ILE_SPEC>
0x5c - FDCAN Interrupt Line Enable Register
gfc: Reg<GFC_SPEC>
0x80 - FDCAN Global Filter Configuration Register
sidfc: Reg<SIDFC_SPEC>
0x84 - FDCAN Standard ID Filter Configuration Register
xidfc: Reg<XIDFC_SPEC>
0x88 - FDCAN Extended ID Filter Configuration Register
xidam: Reg<XIDAM_SPEC>
0x90 - FDCAN Extended ID and Mask Register
hpms: Reg<HPMS_SPEC>
0x94 - FDCAN High Priority Message Status Register
ndat1: Reg<NDAT1_SPEC>
0x98 - FDCAN New Data 1 Register
ndat2: Reg<NDAT2_SPEC>
0x9c - FDCAN New Data 2 Register
rxf0c: Reg<RXF0C_SPEC>
0xa0 - FDCAN Rx FIFO 0 Configuration Register
rxf0s: Reg<RXF0S_SPEC>
0xa4 - FDCAN Rx FIFO 0 Status Register
rxf0a: Reg<RXF0A_SPEC>
0xa8 - CAN Rx FIFO 0 Acknowledge Register
rxbc: Reg<RXBC_SPEC>
0xac - FDCAN Rx Buffer Configuration Register
rxf1c: Reg<RXF1C_SPEC>
0xb0 - FDCAN Rx FIFO 1 Configuration Register
rxf1s: Reg<RXF1S_SPEC>
0xb4 - FDCAN Rx FIFO 1 Status Register
rxf1a: Reg<RXF1A_SPEC>
0xb8 - FDCAN Rx FIFO 1 Acknowledge Register
rxesc: Reg<RXESC_SPEC>
0xbc - FDCAN Rx Buffer Element Size Configuration Register
txbc: Reg<TXBC_SPEC>
0xc0 - FDCAN Tx Buffer Configuration Register
txfqs: Reg<TXFQS_SPEC>
0xc4 - FDCAN Tx FIFO/Queue Status Register
txesc: Reg<TXESC_SPEC>
0xc8 - FDCAN Tx Buffer Element Size Configuration Register
txbrp: Reg<TXBRP_SPEC>
0xcc - FDCAN Tx Buffer Request Pending Register
txbar: Reg<TXBAR_SPEC>
0xd0 - FDCAN Tx Buffer Add Request Register
txbcr: Reg<TXBCR_SPEC>
0xd4 - FDCAN Tx Buffer Cancellation Request Register
txbto: Reg<TXBTO_SPEC>
0xd8 - FDCAN Tx Buffer Transmission Occurred Register
txbcf: Reg<TXBCF_SPEC>
0xdc - FDCAN Tx Buffer Cancellation Finished Register
txbtie: Reg<TXBTIE_SPEC>
0xe0 - FDCAN Tx Buffer Transmission Interrupt Enable Register
txbcie: Reg<TXBCIE_SPEC>
0xe4 - FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
txefc: Reg<TXEFC_SPEC>
0xf0 - FDCAN Tx Event FIFO Configuration Register
txefs: Reg<TXEFS_SPEC>
0xf4 - FDCAN Tx Event FIFO Status Register
txefa: Reg<TXEFA_SPEC>
0xf8 - FDCAN Tx Event FIFO Acknowledge Register
tttmc: Reg<TTTMC_SPEC>
0x100 - FDCAN TT Trigger Memory Configuration Register
ttrmc: Reg<TTRMC_SPEC>
0x104 - FDCAN TT Reference Message Configuration Register
ttocf: Reg<TTOCF_SPEC>
0x108 - FDCAN TT Operation Configuration Register
ttmlm: Reg<TTMLM_SPEC>
0x10c - FDCAN TT Matrix Limits Register
turcf: Reg<TURCF_SPEC>
0x110 - FDCAN TUR Configuration Register
ttocn: Reg<TTOCN_SPEC>
0x114 - FDCAN TT Operation Control Register
ttgtp: Reg<TTGTP_SPEC>
0x118 - FDCAN TT Global Time Preset Register
tttmk: Reg<TTTMK_SPEC>
0x11c - FDCAN TT Time Mark Register
ttir: Reg<TTIR_SPEC>
0x120 - FDCAN TT Interrupt Register
ttie: Reg<TTIE_SPEC>
0x124 - FDCAN TT Interrupt Enable Register
ttils: Reg<TTILS_SPEC>
0x128 - FDCAN TT Interrupt Line Select Register
ttost: Reg<TTOST_SPEC>
0x12c - FDCAN TT Operation Status Register
turna: Reg<TURNA_SPEC>
0x130 - FDCAN TUR Numerator Actual Register
ttlgt: Reg<TTLGT_SPEC>
0x134 - FDCAN TT Local and Global Time Register
ttctc: Reg<TTCTC_SPEC>
0x138 - FDCAN TT Cycle Time and Count Register
ttcpt: Reg<TTCPT_SPEC>
0x13c - FDCAN TT Capture Time Register
ttcsm: Reg<TTCSM_SPEC>
0x140 - FDCAN TT Cycle Sync Mark Register
ttts: Reg<TTTS_SPEC>
0x300 - FDCAN TT Trigger Select Register