Struct stm32_hal2::pac::adc1::RegisterBlock
source · [−]#[repr(C)]pub struct RegisterBlock {Show 33 fields
pub isr: Reg<ISR_SPEC>,
pub ier: Reg<IER_SPEC>,
pub cr: Reg<CR_SPEC>,
pub cfgr: Reg<CFGR_SPEC>,
pub cfgr2: Reg<CFGR2_SPEC>,
pub smpr1: Reg<SMPR1_SPEC>,
pub smpr2: Reg<SMPR2_SPEC>,
pub pcsel: Reg<PCSEL_SPEC>,
pub ltr1: Reg<LTR1_SPEC>,
pub htr1: Reg<HTR1_SPEC>,
pub sqr1: Reg<SQR1_SPEC>,
pub sqr2: Reg<SQR2_SPEC>,
pub sqr3: Reg<SQR3_SPEC>,
pub sqr4: Reg<SQR4_SPEC>,
pub dr: Reg<DR_SPEC>,
pub jsqr: Reg<JSQR_SPEC>,
pub ofr1: Reg<OFR1_SPEC>,
pub ofr2: Reg<OFR2_SPEC>,
pub ofr3: Reg<OFR3_SPEC>,
pub ofr4: Reg<OFR4_SPEC>,
pub jdr1: Reg<JDR1_SPEC>,
pub jdr2: Reg<JDR2_SPEC>,
pub jdr3: Reg<JDR3_SPEC>,
pub jdr4: Reg<JDR4_SPEC>,
pub awd2cr: Reg<AWD2CR_SPEC>,
pub awd3cr: Reg<AWD3CR_SPEC>,
pub ltr2: Reg<LTR2_SPEC>,
pub htr2: Reg<HTR2_SPEC>,
pub ltr3: Reg<LTR3_SPEC>,
pub htr3: Reg<HTR3_SPEC>,
pub difsel: Reg<DIFSEL_SPEC>,
pub calfact: Reg<CALFACT_SPEC>,
pub calfact2: Reg<CALFACT2_SPEC>,
/* private fields */
}
Expand description
Register block
Fields
isr: Reg<ISR_SPEC>
0x00 - ADC interrupt and status register
ier: Reg<IER_SPEC>
0x04 - ADC interrupt enable register
cr: Reg<CR_SPEC>
0x08 - ADC control register
cfgr: Reg<CFGR_SPEC>
0x0c - ADC configuration register 1
cfgr2: Reg<CFGR2_SPEC>
0x10 - ADC configuration register 2
smpr1: Reg<SMPR1_SPEC>
0x14 - ADC sampling time register 1
smpr2: Reg<SMPR2_SPEC>
0x18 - ADC sampling time register 2
pcsel: Reg<PCSEL_SPEC>
0x1c - ADC pre channel selection register
ltr1: Reg<LTR1_SPEC>
0x20 - ADC analog watchdog 1 threshold register
htr1: Reg<HTR1_SPEC>
0x24 - ADC analog watchdog 2 threshold register
sqr1: Reg<SQR1_SPEC>
0x30 - ADC group regular sequencer ranks register 1
sqr2: Reg<SQR2_SPEC>
0x34 - ADC group regular sequencer ranks register 2
sqr3: Reg<SQR3_SPEC>
0x38 - ADC group regular sequencer ranks register 3
sqr4: Reg<SQR4_SPEC>
0x3c - ADC group regular sequencer ranks register 4
dr: Reg<DR_SPEC>
0x40 - ADC group regular conversion data register
jsqr: Reg<JSQR_SPEC>
0x4c - ADC group injected sequencer register
ofr1: Reg<OFR1_SPEC>
0x60 - ADC offset number 1 register
ofr2: Reg<OFR2_SPEC>
0x64 - ADC offset number 2 register
ofr3: Reg<OFR3_SPEC>
0x68 - ADC offset number 3 register
ofr4: Reg<OFR4_SPEC>
0x6c - ADC offset number 4 register
jdr1: Reg<JDR1_SPEC>
0x80 - ADC group injected sequencer rank 1 register
jdr2: Reg<JDR2_SPEC>
0x84 - ADC group injected sequencer rank 2 register
jdr3: Reg<JDR3_SPEC>
0x88 - ADC group injected sequencer rank 3 register
jdr4: Reg<JDR4_SPEC>
0x8c - ADC group injected sequencer rank 4 register
awd2cr: Reg<AWD2CR_SPEC>
0xa0 - ADC analog watchdog 2 configuration register
awd3cr: Reg<AWD3CR_SPEC>
0xa4 - ADC analog watchdog 3 configuration register
ltr2: Reg<LTR2_SPEC>
0xb0 - ADC watchdog lower threshold register 2
htr2: Reg<HTR2_SPEC>
0xb4 - ADC watchdog higher threshold register 2
ltr3: Reg<LTR3_SPEC>
0xb8 - ADC watchdog lower threshold register 3
htr3: Reg<HTR3_SPEC>
0xbc - ADC watchdog higher threshold register 3
difsel: Reg<DIFSEL_SPEC>
0xc0 - ADC channel differential or single-ended mode selection register
calfact: Reg<CALFACT_SPEC>
0xc4 - ADC calibration factors register
calfact2: Reg<CALFACT2_SPEC>
0xc8 - ADC Calibration Factor register 2