Module stm32_hal2::clocks

This module contains clock configurations for various MCUs. They tend to be significantly different from one another, so we’ve feature-gated these files, rather than code within the files, to differentiate families.

See STM32CubeIDE for an interactive editor that’s very useful for seeing what settings are available, and validating them.

See the Reference Manuals for non-interactive visualizations.

Structs

Clocks

Settings used to configure clocks. Create this struct by using its Default::default() implementation, then modify as required, referencing your RM’s clock tree, or Stm32Cube IDE’s interactive clock manager. Apply settings by running .setup().

PllCfg

Configures the speeds, and enable status of an individual PLL. Note that the enable field has no effect for PLL1.

SpeedError

Speed out of limits.

Enums

ApbPrescaler

For use with RCC_APBPPRE1, and RCC_APBPPRE2. Ie, low-speed and high-speed prescalers respectively.

CrsSyncSrc

Select the SYNC signal source. Sets the CRS_CFGR register, SYNCSRC field.

DfsdmSrc

SAI clock input source. Sets RCC_D2CCIP1R register, DFSDM1SEL field.

HclkPrescaler

Division factor for the AHB clock. Also known as AHB Prescaler. See RCC_D1CFGR reg.

HsiDiv

Clock divider for the HSI. See RCC_CR register, HSIDIV field.

InputSrc

Clock input source, also known as system clock switch. Sets RCC_CFGR register, SW field.

PllSrc

SaiSrc

SAI clock input source. Sets RCC_D2CCIP1R register, SAIxSEL field.

StopWuck

Select the system clock used when exiting Stop mode. Sets RCC_CFGR register, STOPWUCK field.

VosRange

Range for the VOS. See H743 RM, section 6.8.6: PWR D3 domain control register. Sets PWR_D3CR, VOS field.