Enum stm32_hal2::adc::ClockMode [−][src]
#[repr(u8)]
pub enum ClockMode {
Async,
SyncDiv1,
SyncDiv2,
SyncDiv4,
}
Expand description
ADC Clock mode (L44 RM, Section 16.4.3) The input clock is the same for the three ADCs and can be selected between two different clock sources (see Figure 40: ADC clock scheme):
- The ADC clock can be a specific clock source. It can be derived from the following clock sources: – The system clock – PLLSAI1 (single ADC implementation) Refer to RCC Section for more information on how to generate ADC dedicated clock. To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be reset.
- The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). In this mode, a programmable divider factor can be selected (/1, 2 or 4 according to bits CKMODE[1:0]). To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be different from “00”.
Variants
Use AHB clock rcc_hclk3. “For option 2), a prescaling factor of 1 (CKMODE[1:0]=01) can be used only if the AHB prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register).”
Use AHB clock rcc_hclk3 divided by 2
Use AHB clock rcc_hclk3 divided by 4