Struct stm32_hal2::pac::tim1::cr1::URS_W [−][src]
pub struct URS_W<'a> { /* fields omitted */ }
Write proxy for field URS
Implementations
impl<'a> URS_W<'a>
[src]
impl<'a> URS_W<'a>
[src]pub fn variant(self, variant: URS_A) -> &'a mut W<u32, Reg<u32, _CR1>>
[src]
Writes variant
to the field
pub fn any_event(self) -> &'a mut W<u32, Reg<u32, _CR1>>
[src]
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
pub fn counter_only(self) -> &'a mut W<u32, Reg<u32, _CR1>>
[src]
Only counter overflow/underflow generates an update interrupt or DMA request
pub fn set_bit(self) -> &'a mut W<u32, Reg<u32, _CR1>>
[src]
Sets the field bit
pub fn clear_bit(self) -> &'a mut W<u32, Reg<u32, _CR1>>
[src]
Clears the field bit
pub fn bit(self, value: bool) -> &'a mut W<u32, Reg<u32, _CR1>>
[src]
Writes raw bits to the field