Enum stm32_hal2::pac::tim1::ccmr2_output::OC3PE_A [−][src]
pub enum OC3PE_A { DISABLED, ENABLED, }
Output compare 3 preload enable
Value on reset: 0
Variants
0: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event
Trait Implementations
impl Clone for OC3PE_A
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impl Clone for OC3PE_A
[src]pub fn clone(&self) -> OC3PE_A
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pub fn clone_from(&mut self, source: &Self)
1.0.0[src]
impl StructuralPartialEq for OC3PE_A
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impl StructuralPartialEq for OC3PE_A
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