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use core::cmp;
use core::marker::PhantomData;
use embedded_hal::blocking::delay::DelayUs;
use crate::fmc::{FmcBank, FmcRegisters};
use crate::FmcPeripheral;
use crate::ral::{fmc, modify_reg};
pub mod device;
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq)]
pub struct NandConfiguration {
pub data_width: u8,
pub column_bits: u8,
}
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq)]
pub struct NandTiming {
pub nce_setup_time: i32,
pub data_setup_time: i32,
pub ale_hold_time: i32,
pub cle_hold_time: i32,
pub ale_to_nre_delay: i32,
pub cle_to_nre_delay: i32,
pub nre_pulse_width_ns: i32,
pub nwe_pulse_width_ns: i32,
pub read_cycle_time_ns: i32,
pub write_cycle_time_ns: i32,
pub nwe_high_to_busy_ns: i32,
}
pub trait NandChip {
const CONFIG: NandConfiguration;
const TIMING: NandTiming;
}
#[allow(missing_debug_implementations)]
pub struct Nand<FMC, IC> {
_chip: PhantomData<IC>,
fmc: FMC,
regs: FmcRegisters,
}
pub trait PinsNand {
const N_DATA: usize;
}
impl<IC: NandChip, FMC: FmcPeripheral> Nand<FMC, IC> {
pub fn new<PINS>(fmc: FMC, _pins: PINS, _chip: IC) -> Self
where
PINS: PinsNand,
{
assert!(
PINS::N_DATA == IC::CONFIG.data_width as usize,
"NAND Data Bus Width mismatch between IC and controller"
);
Nand {
_chip: PhantomData,
fmc,
regs: FmcRegisters::new::<FMC>(),
}
}
pub unsafe fn new_unchecked(fmc: FMC, _chip: IC) -> Self {
Nand {
_chip: PhantomData,
fmc,
regs: FmcRegisters::new::<FMC>(),
}
}
pub fn init<D>(&mut self, delay: &mut D) -> device::NandDevice
where
D: DelayUs<u8>,
{
let fmc_source_ck_hz = self.fmc.source_clock_hz();
let ker_clk_period_ns = 1_000_000_000u32 / fmc_source_ck_hz;
self.fmc.enable();
self.set_features_timings(IC::CONFIG, IC::TIMING, ker_clk_period_ns);
self.fmc.memory_controller_enable();
delay.delay_us(1u8);
unsafe {
let ptr = FmcBank::Bank3.ptr() as *mut u8;
device::NandDevice::init(ptr, IC::CONFIG.column_bits as usize)
}
}
#[allow(non_snake_case)]
fn set_features_timings(
&mut self,
config: NandConfiguration,
timing: NandTiming,
period_ns: u32,
) {
let period_ns = period_ns as i32;
let n_clock_periods = |time_ns: i32| {
(time_ns + period_ns - 1) / period_ns };
let t_CS = timing.nce_setup_time;
let t_DS = timing.data_setup_time;
let t_ALH = timing.ale_hold_time;
let t_CLH = timing.cle_hold_time;
let t_AR = timing.ale_to_nre_delay;
let t_CLR = timing.cle_to_nre_delay;
let t_RP = timing.nre_pulse_width_ns;
let t_WP = timing.nwe_pulse_width_ns;
let t_RC = timing.read_cycle_time_ns;
let t_WC = timing.write_cycle_time_ns;
let t_WB = timing.nwe_high_to_busy_ns;
let setup_time = cmp::max(t_CS, cmp::max(t_AR, t_CLR));
let set = cmp::max(n_clock_periods(setup_time - t_WP), 1) - 1;
assert!(set < 255, "FMC ker clock too fast"); let wait = cmp::max(n_clock_periods(cmp::max(t_RP, t_WP)), 2) - 1;
assert!(wait < 255, "FMC ker clock too fast"); let mut hold = cmp::max(n_clock_periods(cmp::max(t_ALH, t_CLH)), 1);
let cycle_time = n_clock_periods(cmp::max(t_RC, t_WC));
while wait + 1 + hold + set + 1 < cycle_time {
hold += 1;
}
assert!(hold < 255, "FMC ker clock too fast"); let atthold = cmp::max(n_clock_periods(t_WB), 2) - 1;
let atthold = cmp::max(atthold, hold);
assert!(atthold < 255, "FMC ker clock too fast"); let hiz = cmp::max(n_clock_periods(t_CS + t_WP - t_DS), 0);
assert!(hiz < 255, "FMC ker clock too fast"); let ale_to_nre = n_clock_periods(t_AR);
let tar = cmp::max(ale_to_nre - set - 2, 0);
assert!(tar < 16, "FMC ker clock too fast");
let clr_to_nre = n_clock_periods(t_CLR);
let tclr = cmp::max(clr_to_nre - set - 2, 0);
assert!(tclr < 16, "FMC ker clock too fast");
let data_width = match config.data_width {
8 => 0,
16 => 1,
_ => panic!("not possible"),
};
#[rustfmt::skip]
modify_reg!(fmc, self.regs.global(), PCR,
TAR: tar as u32,
TCLR: tclr as u32,
ECCPS: 1, ECCEN: 0, PWID: data_width,
PTYP: 1, PWAITEN: 1 );
#[rustfmt::skip]
modify_reg!(fmc, self.regs.global(), PMEM,
MEMHIZ: hiz as u32,
MEMHOLD: hold as u32,
MEMWAIT: wait as u32,
MEMSET: set as u32);
#[rustfmt::skip]
modify_reg!(fmc, self.regs.global(), PATT,
ATTHIZ: hiz as u32,
ATTHOLD: atthold as u32,
ATTWAIT: wait as u32,
ATTSET: set as u32);
#[rustfmt::skip]
modify_reg!(fmc, self.regs.global(), PCR,
PBKEN: 1);
}
}