Expand description
SDRAM Control Register 1
Structs§
Enums§
- CAS_A
- CAS latency
- MWID_A
- Memory data bus width
- NB_A
- Number of internal banks
- NC_A
- Number of column address bits
- NR_A
- Number of row address bits
- RBURST_
A - Burst read
- RPIPE_A
- Read pipe
- SDCLK_A
- SDRAM clock configuration
- WP_A
- Write protection
Type Aliases§
- CAS_R
- Field
CASreader - CAS latency - CAS_W
- Field
CASwriter - CAS latency - MWID_R
- Field
MWIDreader - Memory data bus width - MWID_W
- Field
MWIDwriter - Memory data bus width - NB_R
- Field
NBreader - Number of internal banks - NB_W
- Field
NBwriter - Number of internal banks - NC_R
- Field
NCreader - Number of column address bits - NC_W
- Field
NCwriter - Number of column address bits - NR_R
- Field
NRreader - Number of row address bits - NR_W
- Field
NRwriter - Number of row address bits - RBURST_
R - Field
RBURSTreader - Burst read - RBURST_
W - Field
RBURSTwriter - Burst read - RPIPE_R
- Field
RPIPEreader - Read pipe - RPIPE_W
- Field
RPIPEwriter - Read pipe - SDCLK_R
- Field
SDCLKreader - SDRAM clock configuration - SDCLK_W
- Field
SDCLKwriter - SDRAM clock configuration - WP_R
- Field
WPreader - Write protection - WP_W
- Field
WPwriter - Write protection