Struct spidev::SpidevOptions

source ·

pub struct SpidevOptions {
    pub bits_per_word: Option<u8>,
    pub max_speed_hz: Option<u32>,
    pub lsb_first: Option<bool>,
    pub spi_mode: Option<SpiModeFlags>,
}

Expand description

Options that control defaults for communication on a device

Individual settings may be overridden via parameters that are specified as part of any individual SpiTransfer when using transfer or transfer_multiple.

Options that are not configured with one of the builder functions will not be modified in the kernel when configure is called.

Fields§

§bits_per_word: Option<u8>§max_speed_hz: Option<u32>§lsb_first: Option<bool>§spi_mode: Option<SpiModeFlags>

Implementations§

source §

impl SpidevOptions

source

pub fn bits_per_word(&mut self, bits_per_word: u8) -> &mut Self

The number of bits in each SPI transfer word

The value zero signifies eight bits.

Examples found in repository ?

examples/spidev-bidir.rs (line 8)

fn main() {
    let mut spidev = Spidev::open("/dev/spidev0.0").unwrap();
    let options = SpidevOptions::new()
        .bits_per_word(8)
        .max_speed_hz(5000)
        .lsb_first(false)
        .mode(SpiModeFlags::SPI_MODE_0)
        .build();
    spidev.configure(&options).unwrap();

    println!("===== Single transfer =========");
    let tx_buf = [0xaa, 0xbb, 0xcc, 0xdd, 0xee];
    let mut rx_buf = [0; 5];
    let mut transfer = SpidevTransfer::read_write(&tx_buf, &mut rx_buf);
    println!("{:?}", spidev.transfer(&mut transfer));

    println!("===== Multi Transfer =========");
    let mut rx_buf1 = [0; 10];
    let tx_buf2 = [0x00, 0x01, 0x02, 0x03];
    let delay_usecs = 10;
    let tx_buf3 = [0xff, 0xfe, 0xfd];
    let mut rx_buf3 = [0; 3];
    let result = {
        let mut transfers = vec![
            SpidevTransfer::read(&mut rx_buf1),
            SpidevTransfer::write(&tx_buf2),
            SpidevTransfer::delay(delay_usecs),
            SpidevTransfer::read_write(&tx_buf3, &mut rx_buf3),
        ];
        spidev.transfer_multiple(&mut transfers)
    };
    match result {
        Ok(_) => {
            println!("Read {:?}", rx_buf1);
            println!("Wrote {:?}", tx_buf2);
            println!("Delayed by {} microseconds", delay_usecs);
            println!("Wrote {:?} and read {:?}", tx_buf3, rx_buf3);
        }
        Err(err) => println!("{:?}", err),
    }
}

source

pub fn max_speed_hz(&mut self, max_speed_hz: u32) -> &mut Self

The maximum SPI transfer speed, in Hz

The controller can’t necessarily assign that specific clock speed.

Examples found in repository ?

examples/spidev-bidir.rs (line 9)

fn main() {
    let mut spidev = Spidev::open("/dev/spidev0.0").unwrap();
    let options = SpidevOptions::new()
        .bits_per_word(8)
        .max_speed_hz(5000)
        .lsb_first(false)
        .mode(SpiModeFlags::SPI_MODE_0)
        .build();
    spidev.configure(&options).unwrap();

    println!("===== Single transfer =========");
    let tx_buf = [0xaa, 0xbb, 0xcc, 0xdd, 0xee];
    let mut rx_buf = [0; 5];
    let mut transfer = SpidevTransfer::read_write(&tx_buf, &mut rx_buf);
    println!("{:?}", spidev.transfer(&mut transfer));

    println!("===== Multi Transfer =========");
    let mut rx_buf1 = [0; 10];
    let tx_buf2 = [0x00, 0x01, 0x02, 0x03];
    let delay_usecs = 10;
    let tx_buf3 = [0xff, 0xfe, 0xfd];
    let mut rx_buf3 = [0; 3];
    let result = {
        let mut transfers = vec![
            SpidevTransfer::read(&mut rx_buf1),
            SpidevTransfer::write(&tx_buf2),
            SpidevTransfer::delay(delay_usecs),
            SpidevTransfer::read_write(&tx_buf3, &mut rx_buf3),
        ];
        spidev.transfer_multiple(&mut transfers)
    };
    match result {
        Ok(_) => {
            println!("Read {:?}", rx_buf1);
            println!("Wrote {:?}", tx_buf2);
            println!("Delayed by {} microseconds", delay_usecs);
            println!("Wrote {:?} and read {:?}", tx_buf3, rx_buf3);
        }
        Err(err) => println!("{:?}", err),
    }
}

source

pub fn lsb_first(&mut self, lsb_first: bool) -> &mut Self

The bit justification used to transfer SPI words

Zero indicates MSB-first; other values indicate the less common LSB-first encoding. In both cases the specified value is right-justified in each word, so that unused (TX) or undefined (RX) bits are in the MSBs.

Examples found in repository ?

examples/spidev-bidir.rs (line 10)

fn main() {
    let mut spidev = Spidev::open("/dev/spidev0.0").unwrap();
    let options = SpidevOptions::new()
        .bits_per_word(8)
        .max_speed_hz(5000)
        .lsb_first(false)
        .mode(SpiModeFlags::SPI_MODE_0)
        .build();
    spidev.configure(&options).unwrap();

    println!("===== Single transfer =========");
    let tx_buf = [0xaa, 0xbb, 0xcc, 0xdd, 0xee];
    let mut rx_buf = [0; 5];
    let mut transfer = SpidevTransfer::read_write(&tx_buf, &mut rx_buf);
    println!("{:?}", spidev.transfer(&mut transfer));

    println!("===== Multi Transfer =========");
    let mut rx_buf1 = [0; 10];
    let tx_buf2 = [0x00, 0x01, 0x02, 0x03];
    let delay_usecs = 10;
    let tx_buf3 = [0xff, 0xfe, 0xfd];
    let mut rx_buf3 = [0; 3];
    let result = {
        let mut transfers = vec![
            SpidevTransfer::read(&mut rx_buf1),
            SpidevTransfer::write(&tx_buf2),
            SpidevTransfer::delay(delay_usecs),
            SpidevTransfer::read_write(&tx_buf3, &mut rx_buf3),
        ];
        spidev.transfer_multiple(&mut transfers)
    };
    match result {
        Ok(_) => {
            println!("Read {:?}", rx_buf1);
            println!("Wrote {:?}", tx_buf2);
            println!("Delayed by {} microseconds", delay_usecs);
            println!("Wrote {:?} and read {:?}", tx_buf3, rx_buf3);
        }
        Err(err) => println!("{:?}", err),
    }
}

source

pub fn mode(&mut self, mode: SpiModeFlags) -> &mut Self

Set the SPI Transfer Mode

Use the constants SPI_MODE_0..SPI_MODE_3; or if you prefer you can combine SPI_CPOL (clock polarity, idle high iff this is set) or SPI_CPHA (clock phase, sample on trailing edge iff this is set) flags.

Note that this API will always prefer to use SPI_IOC_WR_MODE rathern than the 32-bit one to target the greatest number of kernels. SPI_IOC_WR_MODE32 is only present in 3.15+ kernels. SPI_IOC_WR_MODE32 will be used iff bits higher than those in 8bits are provided (e.g. Dual/Quad Tx/Rx).

Examples found in repository ?

examples/spidev-bidir.rs (line 11)

fn main() {
    let mut spidev = Spidev::open("/dev/spidev0.0").unwrap();
    let options = SpidevOptions::new()
        .bits_per_word(8)
        .max_speed_hz(5000)
        .lsb_first(false)
        .mode(SpiModeFlags::SPI_MODE_0)
        .build();
    spidev.configure(&options).unwrap();

    println!("===== Single transfer =========");
    let tx_buf = [0xaa, 0xbb, 0xcc, 0xdd, 0xee];
    let mut rx_buf = [0; 5];
    let mut transfer = SpidevTransfer::read_write(&tx_buf, &mut rx_buf);
    println!("{:?}", spidev.transfer(&mut transfer));

    println!("===== Multi Transfer =========");
    let mut rx_buf1 = [0; 10];
    let tx_buf2 = [0x00, 0x01, 0x02, 0x03];
    let delay_usecs = 10;
    let tx_buf3 = [0xff, 0xfe, 0xfd];
    let mut rx_buf3 = [0; 3];
    let result = {
        let mut transfers = vec![
            SpidevTransfer::read(&mut rx_buf1),
            SpidevTransfer::write(&tx_buf2),
            SpidevTransfer::delay(delay_usecs),
            SpidevTransfer::read_write(&tx_buf3, &mut rx_buf3),
        ];
        spidev.transfer_multiple(&mut transfers)
    };
    match result {
        Ok(_) => {
            println!("Read {:?}", rx_buf1);
            println!("Wrote {:?}", tx_buf2);
            println!("Delayed by {} microseconds", delay_usecs);
            println!("Wrote {:?} and read {:?}", tx_buf3, rx_buf3);
        }
        Err(err) => println!("{:?}", err),
    }
}

source

pub fn build(&self) -> Self

Finalize and build the SpidevOptions

Examples found in repository ?

examples/spidev-bidir.rs (line 12)

fn main() {
    let mut spidev = Spidev::open("/dev/spidev0.0").unwrap();
    let options = SpidevOptions::new()
        .bits_per_word(8)
        .max_speed_hz(5000)
        .lsb_first(false)
        .mode(SpiModeFlags::SPI_MODE_0)
        .build();
    spidev.configure(&options).unwrap();

    println!("===== Single transfer =========");
    let tx_buf = [0xaa, 0xbb, 0xcc, 0xdd, 0xee];
    let mut rx_buf = [0; 5];
    let mut transfer = SpidevTransfer::read_write(&tx_buf, &mut rx_buf);
    println!("{:?}", spidev.transfer(&mut transfer));

    println!("===== Multi Transfer =========");
    let mut rx_buf1 = [0; 10];
    let tx_buf2 = [0x00, 0x01, 0x02, 0x03];
    let delay_usecs = 10;
    let tx_buf3 = [0xff, 0xfe, 0xfd];
    let mut rx_buf3 = [0; 3];
    let result = {
        let mut transfers = vec![
            SpidevTransfer::read(&mut rx_buf1),
            SpidevTransfer::write(&tx_buf2),
            SpidevTransfer::delay(delay_usecs),
            SpidevTransfer::read_write(&tx_buf3, &mut rx_buf3),
        ];
        spidev.transfer_multiple(&mut transfers)
    };
    match result {
        Ok(_) => {
            println!("Read {:?}", rx_buf1);
            println!("Wrote {:?}", tx_buf2);
            println!("Delayed by {} microseconds", delay_usecs);
            println!("Wrote {:?} and read {:?}", tx_buf3, rx_buf3);
        }
        Err(err) => println!("{:?}", err),
    }
}