Crate spi_i2c_hdl_cat 

spi-i2c-hdl-cat

SPI and I2C controllers implemented using hdl-cat categorical hardware description language. Protocol FSMs modeled as Sync<S, I, O> Mealy machines composed via categorical arrows.

Architecture

primitives/    Shared domain newtypes: I2cAddress7, ClockDivider, BaudRate
spi/           SPI domain: modes, transactions, Sync machines
i2c/           I2C domain: conditions, transactions, Sync machines
composition/   MonoidalCategory combinators for multi-device orchestration

Layer 1 (Pure): Domain types, categorical composition, golden models. Zero mut, combinators only.

Layer 2 (HDL): hdl-cat CircuitArrow and Sync<S, I, O> implementations for hardware compilation.

Modules

composition

Bus composition via categorical structure.

error

Project-wide error type.

i2c

I2C protocol domain.

primitives

Domain primitive newtypes shared across SPI and I2C.

simulation

Simulation and Verilog emission for SPI/I2C controllers.

spi

SPI protocol domain.