spdr/lib.rs
1#![no_std]
2#![forbid(unsafe_code)]
3
4//! `spdr` ยท the JESD400-5 DDR5 SPD content decoder.
5//!
6//! The decoder is zero-copy over a byte slice: decoded values borrow directly
7//! from the input SPD image and the crate needs no heap, so it stays embeddable
8//! in firmware and UEFI contexts.
9//!
10//! Phase 1 covers the decode foundation ([`SpdImage`], [`DecodeError`]) and the
11//! identity-and-base configuration block ([`IdentityAndBase`]). Phase 2 adds the
12//! CRC-16 primitive ([`crc16`]) and the base configuration CRC check
13//! ([`verify_base_crc`]), a queryable check that never blocks decoding. Phase 3
14//! adds the base JEDEC timing block ([`Timings`], [`decode_timings`]). Phase 4
15//! adds the module-specific block and the module-type dispatch
16//! ([`ModuleSpecific`], [`decode_module_specific`]): the unbuffered (UDIMM) case
17//! is decoded; SODIMM, RDIMM, and LRDIMM resolve to an explicit not-yet-decoded
18//! result, deferred to later phases gated on real fixtures. Phase 5 adds the
19//! manufacturing information block ([`Manufacturing`], [`decode_manufacturing`]),
20//! including JEP-106 manufacturer resolution. Phase 8 opens the linter, the
21//! validation-beyond-CRC pillar ([`Finding`], [`Severity`], [`lint`]): it reports
22//! structured findings for values that are internally inconsistent even in a
23//! CRC-valid SPD, starting with the capacity-consistency rule. Phase 9a decodes
24//! the vendor overclocking profiles ([`Xmp`], [`Expo`], [`decode_xmp`],
25//! [`decode_expo`]): the rated DDR5 speed lives here, not in the JEDEC base
26//! block, and each section is anchored by its own CRC ([`CrcStatus`]) so an
27//! unconfirmed region is never presented as authoritative.
28
29mod crc;
30mod error;
31mod identity;
32mod lint;
33mod manufacturing;
34mod module;
35mod reader;
36mod timing;
37mod vendor;
38
39pub use crc::{CrcStatus, crc16, verify_base_crc};
40pub use error::DecodeError;
41pub use identity::{
42 BankGroups, BanksPerBankGroup, DensityPerDie, DeviceType, IdentityAndBase, IoWidth, ModuleType,
43 PackageType, SpdRevision, decode_identity_and_base,
44};
45pub use lint::{ClockTimingParam, Finding, Severity, TimingOrder, lint};
46pub use manufacturing::{
47 ManufacturerId, Manufacturing, ManufacturingDate, SerialNumber, decode_manufacturing,
48};
49pub use module::{
50 Millimeters, ModuleSpecific, ReferenceRawCard, UnbufferedModule, decode_module_specific,
51};
52pub use reader::SpdImage;
53pub use timing::{CasLatencies, ClockCycles, Picoseconds, TimingPair, Timings, decode_timings};
54pub use vendor::{
55 Expo, ExpoProfile, Millivolts, RatedTimings, VendorProfiles, Xmp, XmpProfile, decode_expo,
56 decode_vendor_profiles, decode_xmp,
57};