Crate spdr 

spdr · the JESD400-5 DDR5 SPD content decoder.

The decoder is zero-copy over a byte slice: decoded values borrow directly from the input SPD image and the crate needs no heap, so it stays embeddable in firmware and UEFI contexts.

Phase 1 covers the decode foundation (SpdImage, DecodeError) and the identity-and-base configuration block (IdentityAndBase). Phase 2 adds the CRC-16 primitive (crc16) and the base configuration CRC check (verify_base_crc), a queryable check that never blocks decoding. Phase 3 adds the base JEDEC timing block (Timings, decode_timings). Phase 4 adds the module-specific block and the module-type dispatch (ModuleSpecific, decode_module_specific): the unbuffered (UDIMM) case is decoded; SODIMM, RDIMM, and LRDIMM resolve to an explicit not-yet-decoded result, deferred to later phases gated on real fixtures. Phase 5 adds the manufacturing information block (Manufacturing, decode_manufacturing), including JEP-106 manufacturer resolution. Phase 8 opens the linter, the validation-beyond-CRC pillar (Finding, Severity, lint): it reports structured findings for values that are internally inconsistent even in a CRC-valid SPD, starting with the capacity-consistency rule. Phase 9a decodes the vendor overclocking profiles (Xmp, Expo, decode_xmp, decode_expo): the rated DDR5 speed lives here, not in the JEDEC base block, and each section is anchored by its own CRC (CrcStatus) so an unconfirmed region is never presented as authoritative.

Structs

CasLatencies

The set of supported CAS latencies, as a 40-bit mask over the five-byte “CAS Latencies Supported” field. Bit i set means CL 20 + 2*i is supported (DDR5 CAS latencies are even, starting at CL20). The set is held without allocation; iterate it with CasLatencies::iter.

ClockCycles

A timing expressed as a count of clock cycles (nCK). Kept distinct from the absolute-time Picoseconds rather than folded into a single unit.

CrcStatus

The outcome of a CRC verification: a small Copy status, never a hard error.

ExpoProfile

A decoded AMD EXPO profile.

IdentityAndBase

The decoded identity and base SDRAM configuration of an SPD image.

ManufacturerId

A JEP-106 manufacturer identifier: the raw (bank, code) plus a resolved name.

Manufacturing

The decoded manufacturing information block.

ManufacturingDate

A module manufacturing date: a calendar year and an ISO-style week number, each decoded from one BCD byte (the year byte is an offset from 2000).

Millimeters

A length in whole millimetres, the unit DDR5 SPD uses for the module’s physical form fields. The unit is named in the type so no caller has to guess, as crate::Picoseconds does for timings.

Millivolts

A voltage in millivolts, the canonical unit for the profile rails. The unit is named in the type so no caller has to guess, as Picoseconds does for timings. The stored encoding (upper 3 bits = whole volts, lower 5 bits in 50 mV steps) is normalised to millivolts on decode.

Picoseconds

A duration in picoseconds, the canonical fine unit for DDR5 absolute-time timings. The unit is named in the type so no caller has to guess: every absolute-time field is normalised to picoseconds on decode (the tRFC family, stored in nanoseconds, is scaled up by 1000).

RatedTimings

The rated values a vendor profile advertises, shared by XMP and EXPO.

SerialNumber

A module serial number: four raw bytes assembled most-significant-first, the order they are printed in. Rendered as eight uppercase hex digits.

SpdImage

A zero-copy view over a raw SPD byte image.

SpdRevision

SPD revision, decoded from byte 1 as two plain (non-BCD) hex nibbles.

TimingPair

A bank-group-class timing that DDR5 stores as both an absolute-time floor (in picoseconds) and a clock-count floor (in nCK). The effective constraint a controller applies is the larger of the two, so both are preserved here.

Timings

The decoded base JEDEC timing parameters of an SPD image.

UnbufferedModule

The decoded unbuffered (UDIMM) module-specific block.

VendorProfiles

Both vendor-profile regions of an SPD image, decoded together.

XmpProfile

A decoded Intel XMP 3.0 profile.

Enums

BankGroups

Number of bank groups per die, from bits [7:5] of byte 7.

BanksPerBankGroup

Number of banks within each bank group, from bits [2:0] of byte 7.

ClockTimingParam

A clock-quantised timing parameter checked for being a whole multiple of the cycle time. Carried by Finding::NonIntegerClockTiming. tAA is not here: its clock integrality is the operating-CAS-latency check (Finding::NonIntegerCasLatency), so it is not double-counted.

DecodeError

An error produced while decoding an SPD image.

DensityPerDie

SDRAM density per die, from the low five bits of byte 4 (the JEDEC table).

DeviceType

DRAM device type, from byte 2 (the whole-byte “key byte 1”).

Expo

The AMD EXPO region: either absent (no magic) or present with its block CRC and the populated profiles.

Finding

A single lint finding: one detected inconsistency, carrying the structured values that produced it rather than a preformatted message.

IoWidth

SDRAM I/O device width (DQ pins per device), from bits [7:5] of byte 6.

ModuleSpecific

The module-specific decode, dispatched on the module type (byte 3).

ModuleType

Base module type, from the low nibble of byte 3.

PackageType

SDRAM package construction, from bits [7:5] of byte 4.

ReferenceRawCard

The reference raw card a module is built from (byte 232).

Severity

The severity of a lint Finding.

TimingOrder

A JEDEC timing ordering that must hold between two absolute-time parameters. Carried by Finding::TimingOrderingViolation so the finding names which relation was violated without a preformatted message.

Xmp

The Intel XMP 3.0 region: either absent (no magic) or present with its header CRC and the enabled profiles.

Functions

crc16

Compute the JEDEC SPD CRC-16 over bytes.

decode_expo

Decode the AMD EXPO region from a raw SPD image.

decode_identity_and_base

Decode the identity and base SDRAM configuration from a raw SPD image.

decode_manufacturing

Decode the manufacturing information block from a raw SPD image.

decode_module_specific

Decode the module-specific block from a raw SPD image.

decode_timings

Decode the base JEDEC timing block from a raw SPD image.

decode_vendor_profiles

Decode both vendor-profile regions (XMP 3.0 and EXPO) from a raw SPD image.

decode_xmp

Decode the Intel XMP 3.0 region from a raw SPD image.

lint

Lint an SPD image, reporting each Finding to sink.

verify_base_crc

Verify the base configuration CRC of an SPD image.