sparreal_kernel/hal_al/
mmu.rs

1use core::fmt::Debug;
2
3pub use page_table_generic::{Access, PagingError, PhysAddr};
4
5pub use crate::mem::{Phys, Virt};
6
7#[derive(Clone, Copy, PartialEq, Eq)]
8pub enum AccessSetting {
9    Read,
10    ReadWrite,
11    ReadExecute,
12    ReadWriteExecute,
13}
14impl core::fmt::Debug for AccessSetting {
15    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
16        match self {
17            AccessSetting::Read => write!(f, "R--"),
18            AccessSetting::ReadWrite => write!(f, "RW-"),
19            AccessSetting::ReadExecute => write!(f, "R-X"),
20            AccessSetting::ReadWriteExecute => write!(f, "RWX"),
21        }
22    }
23}
24
25#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
26pub enum CacheSetting {
27    /// Normal memory, cacheable, write-back
28    Normal,
29    /// Device memory, non-cacheable
30    Device,
31    /// Non-cacheable memory, strongly ordered
32    NonCacheable,
33    /// Per-CPU cacheable
34    PerCpu,
35}
36
37#[derive(Debug, Clone, Copy)]
38pub struct PageTableRef {
39    pub id: usize,
40    pub addr: Phys<u8>,
41}
42
43#[trait_ffi::def_extern_trait(not_def_impl)]
44pub trait Mmu {
45    /// Called once after memory management is ready.
46    fn setup();
47    fn page_size() -> usize;
48    fn kimage_va_offset() -> usize;
49
50    fn new_table(alloc: &mut dyn Access) -> Result<PageTableRef, PagingError>;
51    fn release_table(table: PageTableRef, alloc: &mut dyn Access);
52    fn get_kernel_table() -> PageTableRef;
53    fn set_kernel_table(new_table: PageTableRef);
54    fn table_map(
55        table: PageTableRef,
56        alloc: &mut dyn Access,
57        config: &MapConfig,
58    ) -> Result<(), PagingError>;
59}
60
61#[derive(Debug, Clone)]
62pub struct MapConfig {
63    pub name: &'static str,
64    pub va_start: Virt<u8>,
65    pub pa_start: Phys<u8>,
66    pub size: usize,
67    pub access: AccessSetting,
68    pub cache: CacheSetting,
69}
sparreal_kernel/hal_al/mmu.rs

sparreal_kernel/hal_al/
mmu.rs
