sp1_core_executor/
register.rs

1//! Registers for the SP1 zkVM.
2
3use sp1_jit::{RiscOperand, RiscRegister};
4
5/// The number of registers.
6pub const NUM_REGISTERS: usize = 32;
7
8/// A register stores a 32-bit value used by operations.
9#[derive(Debug, Clone, Copy, PartialEq)]
10pub enum Register {
11    /// %x0
12    X0 = 0,
13    /// %x1
14    X1 = 1,
15    /// %x2
16    X2 = 2,
17    /// %x3
18    X3 = 3,
19    /// %x4
20    X4 = 4,
21    /// %x5
22    X5 = 5,
23    /// %x6
24    X6 = 6,
25    /// %x7
26    X7 = 7,
27    /// %x8
28    X8 = 8,
29    /// %x9
30    X9 = 9,
31    /// %x10
32    X10 = 10,
33    /// %x11
34    X11 = 11,
35    /// %x12
36    X12 = 12,
37    /// %x13
38    X13 = 13,
39    /// %x14
40    X14 = 14,
41    /// %x15
42    X15 = 15,
43    /// %x16
44    X16 = 16,
45    /// %x17
46    X17 = 17,
47    /// %x18
48    X18 = 18,
49    /// %x19
50    X19 = 19,
51    /// %x20
52    X20 = 20,
53    /// %x21
54    X21 = 21,
55    /// %x22
56    X22 = 22,
57    /// %x23
58    X23 = 23,
59    /// %x24
60    X24 = 24,
61    /// %x25
62    X25 = 25,
63    /// %x26
64    X26 = 26,
65    /// %x27
66    X27 = 27,
67    /// %x28
68    X28 = 28,
69    /// %x29
70    X29 = 29,
71    /// %x30
72    X30 = 30,
73    /// %x31
74    X31 = 31,
75}
76
77impl Register {
78    /// Create a new register from a u8.
79    ///
80    /// # Panics
81    ///
82    /// This function will panic if the register is invalid.
83    #[inline]
84    #[must_use]
85    pub fn from_u8(value: u8) -> Self {
86        match value {
87            0 => Register::X0,
88            1 => Register::X1,
89            2 => Register::X2,
90            3 => Register::X3,
91            4 => Register::X4,
92            5 => Register::X5,
93            6 => Register::X6,
94            7 => Register::X7,
95            8 => Register::X8,
96            9 => Register::X9,
97            10 => Register::X10,
98            11 => Register::X11,
99            12 => Register::X12,
100            13 => Register::X13,
101            14 => Register::X14,
102            15 => Register::X15,
103            16 => Register::X16,
104            17 => Register::X17,
105            18 => Register::X18,
106            19 => Register::X19,
107            20 => Register::X20,
108            21 => Register::X21,
109            22 => Register::X22,
110            23 => Register::X23,
111            24 => Register::X24,
112            25 => Register::X25,
113            26 => Register::X26,
114            27 => Register::X27,
115            28 => Register::X28,
116            29 => Register::X29,
117            30 => Register::X30,
118            31 => Register::X31,
119            _ => panic!("invalid register {value}"),
120        }
121    }
122}
123
124impl From<Register> for RiscOperand {
125    fn from(value: Register) -> Self {
126        RiscOperand::Register(value.into())
127    }
128}
129
130impl From<Register> for RiscRegister {
131    fn from(value: Register) -> Self {
132        match value {
133            Register::X0 => RiscRegister::X0,
134            Register::X1 => RiscRegister::X1,
135            Register::X2 => RiscRegister::X2,
136            Register::X3 => RiscRegister::X3,
137            Register::X4 => RiscRegister::X4,
138            Register::X5 => RiscRegister::X5,
139            Register::X6 => RiscRegister::X6,
140            Register::X7 => RiscRegister::X7,
141            Register::X8 => RiscRegister::X8,
142            Register::X9 => RiscRegister::X9,
143            Register::X10 => RiscRegister::X10,
144            Register::X11 => RiscRegister::X11,
145            Register::X12 => RiscRegister::X12,
146            Register::X13 => RiscRegister::X13,
147            Register::X14 => RiscRegister::X14,
148            Register::X15 => RiscRegister::X15,
149            Register::X16 => RiscRegister::X16,
150            Register::X17 => RiscRegister::X17,
151            Register::X18 => RiscRegister::X18,
152            Register::X19 => RiscRegister::X19,
153            Register::X20 => RiscRegister::X20,
154            Register::X21 => RiscRegister::X21,
155            Register::X22 => RiscRegister::X22,
156            Register::X23 => RiscRegister::X23,
157            Register::X24 => RiscRegister::X24,
158            Register::X25 => RiscRegister::X25,
159            Register::X26 => RiscRegister::X26,
160            Register::X27 => RiscRegister::X27,
161            Register::X28 => RiscRegister::X28,
162            Register::X29 => RiscRegister::X29,
163            Register::X30 => RiscRegister::X30,
164            Register::X31 => RiscRegister::X31,
165        }
166    }
167}
sp1_core_executor/register.rs

sp1_core_executor/
register.rs
