sp1_core_executor/events/
instr.rs

1use serde::{Deserialize, Serialize};
2
3use crate::Opcode;
4
5use super::MemoryRecordEnum;
6
7/// Alu Instruction Event.
8///
9/// This object encapsulated the information needed to prove a RISC-V ALU operation.
10#[derive(Debug, Clone, Copy, Serialize, Deserialize)]
11#[repr(C)]
12pub struct AluEvent {
13    /// The program counter.
14    pub pc: u32,
15    /// The opcode.
16    pub opcode: Opcode,
17    /// The first operand value.
18    pub a: u32,
19    /// The second operand value.
20    pub b: u32,
21    /// The third operand value.
22    pub c: u32,
23    /// Whether the first operand is register 0.
24    pub op_a_0: bool,
25}
26
27impl AluEvent {
28    /// Create a new [`AluEvent`].
29    #[must_use]
30    pub fn new(pc: u32, opcode: Opcode, a: u32, b: u32, c: u32, op_a_0: bool) -> Self {
31        Self { pc, opcode, a, b, c, op_a_0 }
32    }
33}
34
35/// Memory Instruction Event.
36///
37/// This object encapsulated the information needed to prove a RISC-V memory operation.
38#[derive(Debug, Clone, Copy, Serialize, Deserialize)]
39#[repr(C)]
40pub struct MemInstrEvent {
41    /// The shard.
42    pub shard: u32,
43    /// The clk.
44    pub clk: u32,
45    /// The program counter.
46    pub pc: u32,
47    /// The opcode.
48    pub opcode: Opcode,
49    /// The first operand value.
50    pub a: u32,
51    /// The second operand value.
52    pub b: u32,
53    /// The third operand value.
54    pub c: u32,
55    /// Whether the first operand is register 0.
56    pub op_a_0: bool,
57    /// The memory access record for memory operations.
58    pub mem_access: MemoryRecordEnum,
59}
60
61impl MemInstrEvent {
62    /// Create a new [`MemInstrEvent`].
63    #[must_use]
64    #[allow(clippy::too_many_arguments)]
65    pub fn new(
66        shard: u32,
67        clk: u32,
68        pc: u32,
69        opcode: Opcode,
70        a: u32,
71        b: u32,
72        c: u32,
73        op_a_0: bool,
74        mem_access: MemoryRecordEnum,
75    ) -> Self {
76        Self { shard, clk, pc, opcode, a, b, c, op_a_0, mem_access }
77    }
78}
79
80/// Branch Instruction Event.
81///
82/// This object encapsulated the information needed to prove a RISC-V branch operation.
83#[derive(Debug, Clone, Copy, Serialize, Deserialize)]
84#[repr(C)]
85pub struct BranchEvent {
86    /// The program counter.
87    pub pc: u32,
88    /// The next program counter.
89    pub next_pc: u32,
90    /// The opcode.
91    pub opcode: Opcode,
92    /// The first operand value.
93    pub a: u32,
94    /// The second operand value.
95    pub b: u32,
96    /// The third operand value.
97    pub c: u32,
98    /// Whether the first operand is register 0.
99    pub op_a_0: bool,
100}
101
102impl BranchEvent {
103    /// Create a new [`BranchEvent`].
104    #[must_use]
105    #[allow(clippy::too_many_arguments)]
106    pub fn new(
107        pc: u32,
108        next_pc: u32,
109        opcode: Opcode,
110        a: u32,
111        b: u32,
112        c: u32,
113        op_a_0: bool,
114    ) -> Self {
115        Self { pc, next_pc, opcode, a, b, c, op_a_0 }
116    }
117}
118
119/// Jump Instruction Event.
120///
121/// This object encapsulated the information needed to prove a RISC-V jump operation.
122#[derive(Debug, Clone, Copy, Serialize, Deserialize)]
123#[repr(C)]
124pub struct JumpEvent {
125    /// The program counter.
126    pub pc: u32,
127    /// The next program counter.
128    pub next_pc: u32,
129    /// The opcode.
130    pub opcode: Opcode,
131    /// The first operand value.
132    pub a: u32,
133    /// The second operand value.
134    pub b: u32,
135    /// The third operand value.
136    pub c: u32,
137    /// Whether the first operand is register 0.
138    pub op_a_0: bool,
139}
140
141impl JumpEvent {
142    /// Create a new [`JumpEvent`].
143    #[must_use]
144    #[allow(clippy::too_many_arguments)]
145    pub fn new(
146        pc: u32,
147        next_pc: u32,
148        opcode: Opcode,
149        a: u32,
150        b: u32,
151        c: u32,
152        op_a_0: bool,
153    ) -> Self {
154        Self { pc, next_pc, opcode, a, b, c, op_a_0 }
155    }
156}
157/// AUIPC Instruction Event.
158///
159/// This object encapsulated the information needed to prove a RISC-V AUIPC operation.
160#[derive(Debug, Clone, Copy, Serialize, Deserialize)]
161#[repr(C)]
162pub struct AUIPCEvent {
163    /// The program counter.
164    pub pc: u32,
165    /// The opcode.
166    pub opcode: Opcode,
167    /// The first operand value.
168    pub a: u32,
169    /// The second operand value.
170    pub b: u32,
171    /// The third operand value.
172    pub c: u32,
173    /// Whether the first operand is register 0.
174    pub op_a_0: bool,
175}
176
177impl AUIPCEvent {
178    /// Create a new [`AUIPCEvent`].
179    #[must_use]
180    pub fn new(pc: u32, opcode: Opcode, a: u32, b: u32, c: u32, op_a_0: bool) -> Self {
181        Self { pc, opcode, a, b, c, op_a_0 }
182    }
183}
sp1_core_executor/events/instr.rs

sp1_core_executor/events/
instr.rs
