softcore_asm_rv64/
lib.rs

1//! Softcore Assembly Macro
2
3/// The Softcore Assembly macro
4///
5/// This macro translates RISC-V inline assembly into pure Rust code, by using the `softcore_rv64`
6/// CPU model.
7pub use softcore_asm_macro::asm;
8
9/// Softcore RV64
10///
11/// A Rust model of a RISC-V 64 bits CPU, automatically translated from the official [Sail
12/// specification](https://github.com/riscv/sail-riscv).
13pub use softcore_rv64;
14
15// —————————————————————————— Register Conversion ——————————————————————————— //
16
17/// A trait for types that can be passed through registers
18pub trait FromRegister {
19    fn from_register(value: u64) -> Self;
20}
21
22impl FromRegister for u64 {
23    fn from_register(value: u64) -> Self {
24        value
25    }
26}
27
28impl FromRegister for u32 {
29    fn from_register(value: u64) -> Self {
30        value as u32
31    }
32}
33
34impl FromRegister for usize {
35    fn from_register(value: u64) -> Self {
36        value as usize
37    }
38}
39
40impl<A> FromRegister for *const A {
41    fn from_register(value: u64) -> Self {
42        value as usize as *const _
43    }
44}
45
46impl<A> FromRegister for *mut A {
47    fn from_register(value: u64) -> Self {
48        value as usize as *mut _
49    }
50}
51
52// —————————————————————————————— Trap Handler —————————————————————————————— //
53
54pub fn handle_trap(addr: u64, trap_handlers: &[extern "C" fn()]) {
55    for handler in trap_handlers {
56        if *handler as *const () as u64 == addr {
57            handler();
58            return;
59        }
60    }
61
62    panic!("Trapped with no valid trap handler registered");
63}
softcore_asm_rv64/lib.rs

softcore_asm_rv64/
lib.rs
