snarkvm_synthesizer_program/logic/instruction/operand/
bytes.rs

1// Copyright (c) 2019-2025 Provable Inc.
2// This file is part of the snarkVM library.
3
4// Licensed under the Apache License, Version 2.0 (the "License");
5// you may not use this file except in compliance with the License.
6// You may obtain a copy of the License at:
7
8// http://www.apache.org/licenses/LICENSE-2.0
9
10// Unless required by applicable law or agreed to in writing, software
11// distributed under the License is distributed on an "AS IS" BASIS,
12// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13// See the License for the specific language governing permissions and
14// limitations under the License.
15
16use super::*;
17
18impl<N: Network> FromBytes for Operand<N> {
19    fn read_le<R: Read>(mut reader: R) -> IoResult<Self> {
20        match u8::read_le(&mut reader)? {
21            0 => Ok(Self::Literal(Literal::read_le(&mut reader)?)),
22            1 => Ok(Self::Register(Register::read_le(&mut reader)?)),
23            2 => Ok(Self::ProgramID(ProgramID::read_le(&mut reader)?)),
24            3 => Ok(Self::Signer),
25            4 => Ok(Self::Caller),
26            5 => Ok(Self::BlockHeight),
27            6 => Ok(Self::NetworkID),
28            variant => Err(error(format!("Failed to deserialize operand variant {variant}"))),
29        }
30    }
31}
32
33impl<N: Network> ToBytes for Operand<N> {
34    fn write_le<W: Write>(&self, mut writer: W) -> IoResult<()> {
35        match self {
36            Self::Literal(literal) => {
37                0u8.write_le(&mut writer)?;
38                literal.write_le(&mut writer)
39            }
40            Self::Register(register) => {
41                1u8.write_le(&mut writer)?;
42                register.write_le(&mut writer)
43            }
44            Self::ProgramID(program_id) => {
45                2u8.write_le(&mut writer)?;
46                program_id.write_le(&mut writer)
47            }
48            Self::Signer => 3u8.write_le(&mut writer),
49            Self::Caller => 4u8.write_le(&mut writer),
50            Self::BlockHeight => 5u8.write_le(&mut writer),
51            Self::NetworkID => 6u8.write_le(&mut writer),
52        }
53    }
54}
snarkvm_synthesizer_program/logic/instruction/operand/bytes.rs

snarkvm_synthesizer_program/logic/instruction/operand/
bytes.rs
