Expand description
Assembly instructions
§Absence of PAUSE instruction
SiFive cores may have PAUSE instruction implemented, which is also defined in RISC-V extension
Zihintpause. This extension is adapted to core::hint::spin_loop() function in Rust core crate,
and thus not implemented separately in platform specific assembly instruction module.
On hardware implementation of SiFive platform, PAUSE instruction causes a stall of up to 32 cycles or until a cache eviction occurs, whichever comes first.
Functions§
- cdiscard_
d_ l1_ all - CDISCARD.D.L1 x0, L1 data cache full-cache invalidate instruction
- cdiscard_
d_ l1_ va - CDISCARD.D.L1 rs1, L1 data cache invalidate virtual address instruction
- cease⚠
- CEASE, core halt instruction
- cflush_
d_ l1_ all - CFLUSH.D.L1 x0, L1 data cache full-cache flush instruction
- cflush_
d_ l1_ va - CFLUSH.D.L1 rs1, L1 data cache flush virtual address instruction
- mnret⚠
- MNRET, non-maskable interrupt return instruction