sifive_core/
lib.rs

1//! Low level access to SiFive RISC-V processor cores
2//!
3//! This crate provides:
4//!
5//! - Access to core SiFive CSRs like bpm and feature disable;
6//! - Access to assemble instructions like CEASE and cache control instructions;
7//! - High level wrapper for handling SiFive platform features.
8#![no_std]
9
10pub mod asm;
11#[doc(hidden)] // hide by now, API has not been decided yet
12pub mod feature;
13pub mod register;