Expand description
Hardware pointer masking platform detection and operations.
Supports:
- ARM64 TBI (Top Byte Ignore): Always available on ARM64. Hardware ignores the top byte of pointers, giving us 8 bits for GC metadata.
- x86-64 LAM (Linear Address Masking): Available on recent Intel/AMD. Masks bits 62:57 (LAM57) or 62:48 (LAM48).
- Software fallback: Manually AND-mask before dereferencing.
§Pointer format
ARM TBI: [COLOR:2][GEN:1][unused:5][ADDRESS:56]
x86-64 LAM: [0][COLOR:2][GEN:1][unused:3][ADDRESS:57]
Fallback: Same format, software AND mask before deref§Integration with NaN-boxing
NaN-boxing uses a 48-bit PAYLOAD_MASK which already strips upper bits. GC metadata lives in bits 48-55 which are zeroed by PAYLOAD_MASK. So existing ValueWord pointer extraction automatically strips GC tags. Tags are only relevant inside the GC itself.
Enums§
- Masking
Mode - Detected pointer masking mode.
Functions§
- cached_
masking_ mode - Get the cached masking mode, detecting on first call.
- detect_
masking_ mode - Detect the best available pointer masking mode for this platform.
- has_
x86_ lam - Check if x86-64 LAM is available (runtime-detected).
- mask_
ptr - Strip metadata bits from a tagged pointer, returning the raw address.
- read_
color - Read the color from a tagged pointer.
- read_
generation - Read the generation from a tagged pointer.
- tag_ptr
- Tag a raw pointer with GC metadata (color and generation).