Module debug_loop

Module debug_loop 

Source
Expand description

Structs§

DebugLoopSpec
You can read this register and get debug_loop::R. You can reset, write, write_with_zero this register using debug_loop::W. You can also modify this register. See API.

Type Aliases§

Ad2daLoopBackR
Field AD2DA_LOOP_BACK reader - RX–>TX Loop debug control: 0: disable 1: enable, internally connect RX Resampled PCM to TX Resample PCM input
Ad2daLoopBackW
Field AD2DA_LOOP_BACK writer - RX–>TX Loop debug control: 0: disable 1: enable, internally connect RX Resampled PCM to TX Resample PCM input
Da2adLoopBackR
Field DA2AD_LOOP_BACK reader - TX–>RX Loop debug control: 0: disable 1: enable, internally connect TX SDTO to RX SDTI
Da2adLoopBackW
Field DA2AD_LOOP_BACK writer - TX–>RX Loop debug control: 0: disable 1: enable, internally connect TX SDTO to RX SDTI
R
Register DEBUG_LOOP reader
Rsvd2R
Field RSVD2 reader -
Rsvd2W
Field RSVD2 writer -
Rsvd3R
Field RSVD3 reader -
Rsvd3W
Field RSVD3 writer -
RsvdR
Field RSVD reader -
RsvdW
Field RSVD writer -
SpClkDivR
Field SP_CLK_DIV reader - sp clock divider value
SpClkDivUpdateR
Field SP_CLK_DIV_UPDATE reader - update sp clock divider
SpClkDivUpdateW
Field SP_CLK_DIV_UPDATE writer - update sp clock divider
SpClkDivW
Field SP_CLK_DIV writer - sp clock divider value
SpClkSelR
Field SP_CLK_SEL reader - clock select 0: xtal clock 1: pll clock
SpClkSelW
Field SP_CLK_SEL writer - clock select 0: xtal clock 1: pll clock
W
Register DEBUG_LOOP writer