Module top_ctrl 

Top Control Register

Structs

TopCtrlSpec

Top Control Register

Type Aliases

DssR

Field DSS reader - SSP Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits

DssW

Field DSS writer - SSP Work data size, register bits value 0~31 indicated data size 1~32 bits, usually use data size 8bits, 16bits, 24bits, 32bits

FrfR

Field FRF reader - Frame Format 0x0 = Motorola* Serial Peripheral Interface (SPI) 0x1 = Texas Instruments* Synchronous Serial Protocol (SSP) 0x2 = National Semiconductor Microwire* 0x3 = Programmable Serial Protocol (PSP)

FrfW

Field FRF writer - Frame Format 0x0 = Motorola* Serial Peripheral Interface (SPI) 0x1 = Texas Instruments* Synchronous Serial Protocol (SSP) 0x2 = National Semiconductor Microwire* 0x3 = Programmable Serial Protocol (PSP)

HoldFrameLowR

Field HOLD_FRAME_LOW reader - Hold Frame Low Control 1=After this field is set to 1 and the SSP is operating in master mode, the output frame clock ssp_sfrm_gpio will hold low. Used for SPI and NMW Format Rx FIFO Auto Full Control, which makes the frame clock is still low during there’s no bit clock, or the data transfers before the stop clock will be discarded.

HoldFrameLowW

Field HOLD_FRAME_LOW writer - Hold Frame Low Control 1=After this field is set to 1 and the SSP is operating in master mode, the output frame clock ssp_sfrm_gpio will hold low. Used for SPI and NMW Format Rx FIFO Auto Full Control, which makes the frame clock is still low during there’s no bit clock, or the data transfers before the stop clock will be discarded.

IfsR

Field IFS reader - Invert Frame Signal 0 = SSPSFRMx polarity is determined by the PSP polarity bits 1 = SSPSFRMx will be inverted from normal-SSPSFRMx (as defined by the PSP polarity bits). (Works in all frame formats: SPI, SSP, and PSP)

IfsW

Field IFS writer - Invert Frame Signal 0 = SSPSFRMx polarity is determined by the PSP polarity bits 1 = SSPSFRMx will be inverted from normal-SSPSFRMx (as defined by the PSP polarity bits). (Works in all frame formats: SPI, SSP, and PSP)

R

Register TOP_CTRL reader

Rsvd2R

Field RSVD2 reader -

Rsvd2W

Field RSVD2 writer -

RsvdR

Field RSVD reader -

RsvdW

Field RSVD writer -

ScfrR

Field SCFR reader - Slave Clock Free Running 0 = Clock input to SSPSCLKx is continuously running 1 = Clock input to SSPSCLKx is only active during data transfers.

ScfrW

Field SCFR writer - Slave Clock Free Running 0 = Clock input to SSPSCLKx is continuously running 1 = Clock input to SSPSCLKx is only active during data transfers.

SclkdirR

Field SCLKDIR reader - SSP Serial Bit Rate Clock (SSPSCLKx) Direction 0 = Master mode, SSPx port drives SSPSCLKx 1 = Slave mode, SSPx port receives SSPSCLKx

SclkdirW

Field SCLKDIR writer - SSP Serial Bit Rate Clock (SSPSCLKx) Direction 0 = Master mode, SSPx port drives SSPSCLKx 1 = Slave mode, SSPx port receives SSPSCLKx

SfrmdirR

Field SFRMDIR reader - SSP Frame (SSPSFRMx) Direction 0 = Master mode, SSPx port drives SSPSFRMx 1 = Slave mode, SSPx port receives SSPSFRMx

SfrmdirW

Field SFRMDIR writer - SSP Frame (SSPSFRMx) Direction 0 = Master mode, SSPx port drives SSPSFRMx 1 = Slave mode, SSPx port receives SSPSFRMx

SphR

Field SPH reader - Motorola SPI SSPSCLK phase setting 0 = SSPSCLKx is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame 1 = SSPSCLKx is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame

SphW

Field SPH writer - Motorola SPI SSPSCLK phase setting 0 = SSPSCLKx is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame 1 = SSPSCLKx is inactive until 1/2 cycle after the start of a frame and active until one cycle before the end of a frame

SpoR

Field SPO reader - Motorola SPI SSPSCLK Polarity Setting 0 = The inactive or idle state of SSPSCLKx is low 1 = The inactive or idle state of SSPSCLKx is high

SpoW

Field SPO writer - Motorola SPI SSPSCLK Polarity Setting 0 = The inactive or idle state of SSPSCLKx is low 1 = The inactive or idle state of SSPSCLKx is high

SseR

Field SSE reader - Synchronous Serial Port Enable 0 = SSPx port is disabled 1 = SSPx port is enabled

SseW

Field SSE writer - Synchronous Serial Port Enable 0 = SSPx port is disabled 1 = SSPx port is enabled

TrailR

Field TRAIL reader - Trailing Byte 0 = Trailing bytes are handled by SW 1 = Trailing bytes are handled by DMA bursts

TrailW

Field TRAIL writer - Trailing Byte 0 = Trailing bytes are handled by SW 1 = Trailing bytes are handled by DMA bursts

TteR

Field TTE reader - TXD Three-State Enable 0 = TXDx output signal is not three-stated 1 = TXD is three-stated when not transmitting data

TteW

Field TTE writer - TXD Three-State Enable 0 = TXDx output signal is not three-stated 1 = TXD is three-stated when not transmitting data

TtelpR

Field TTELP reader - TXD Three-state Enable On Last Phase 0 = TXDx is three-stated 1/2 clock cycle after the beginning of the LSB 1 = TXDx output signal is three-stated on the clock edge that ends the LSB

TtelpW

Field TTELP writer - TXD Three-state Enable On Last Phase 0 = TXDx is three-stated 1/2 clock cycle after the beginning of the LSB 1 = TXDx output signal is three-stated on the clock edge that ends the LSB

W

Register TOP_CTRL writer