Module fifo_ctrl 

FIFO Control Register

Structs

FifoCtrlSpec

FIFO Control Register

Type Aliases

EfwrR

Field EFWR reader - Enable FIFO Write/read (Test Mode Bit) 0 = FIFO write/read special function is disabled (normal SSPx operational mode) 1 = FIFO write/read special function is enabled

EfwrW

Field EFWR writer - Enable FIFO Write/read (Test Mode Bit) 0 = FIFO write/read special function is disabled (normal SSPx operational mode) 1 = FIFO write/read special function is enabled

FpckeR

Field FPCKE reader - FIFO Packing Enable 0 = FIFO packing mode disabled 1 = FIFO packing mode enabled

FpckeW

Field FPCKE writer - FIFO Packing Enable 0 = FIFO packing mode disabled 1 = FIFO packing mode enabled

R

Register FIFO_CTRL reader

RftR

Field RFT reader - RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1.

RftW

Field RFT writer - RXFIFO Trigger Threshold This field sets the threshold level at which RXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1.

RsreR

Field RSRE reader - Receive Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled

RsreW

Field RSRE writer - Receive Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled

RsvdR

Field RSVD reader -

RsvdW

Field RSVD writer -

RxfifoAutoFullCtrlR

Field RXFIFO_AUTO_FULL_CTRL reader - Rx FIFO Auto Full Control =1After this field is set to 1 and the SSP is operating in master mode, the SSP FSM returns to IDLE state and stops the ssp_sclk_gpio. When Rx FIFO is full, the SSP FSM continues transferring data after the Rx FIFO is not full. This field is used to avoid an Rx FIFO overrun issue. 1= Enable Rx FIFO auto full control

RxfifoAutoFullCtrlW

Field RXFIFO_AUTO_FULL_CTRL writer - Rx FIFO Auto Full Control =1After this field is set to 1 and the SSP is operating in master mode, the SSP FSM returns to IDLE state and stops the ssp_sclk_gpio. When Rx FIFO is full, the SSP FSM continues transferring data after the Rx FIFO is not full. This field is used to avoid an Rx FIFO overrun issue. 1= Enable Rx FIFO auto full control

RxfifoRdEndianR

Field RXFIFO_RD_ENDIAN reader - apb_prdata Read from Rx FIFO Endian 0x0 = apb_prdata[31:0] = rxfifo_wdata[31:0] 0x1 = apb_prdata[31:0] = {rxfifo_wdata[15:0], rxfifo_wdata[31:16]} 0x2 = apb_prdata[31:0]= {rxfifo_wdata[7:0], rxfifo_wdata[15:8], rxfifo_wdata[23:16], rxfifo_wdata[31:24]} 0x3 = apb_prdata[31:0]= {rxfifo_wdata[23:16], rxfifo_wdata[31:24], rxfifo_wdata[7:0], rxfifo_wdata[15:8]}

RxfifoRdEndianW

Field RXFIFO_RD_ENDIAN writer - apb_prdata Read from Rx FIFO Endian 0x0 = apb_prdata[31:0] = rxfifo_wdata[31:0] 0x1 = apb_prdata[31:0] = {rxfifo_wdata[15:0], rxfifo_wdata[31:16]} 0x2 = apb_prdata[31:0]= {rxfifo_wdata[7:0], rxfifo_wdata[15:8], rxfifo_wdata[23:16], rxfifo_wdata[31:24]} 0x3 = apb_prdata[31:0]= {rxfifo_wdata[23:16], rxfifo_wdata[31:24], rxfifo_wdata[7:0], rxfifo_wdata[15:8]}

StrfR

Field STRF reader - Select FIFO For Efwr (Test Mode Bit) Only when the <Enable FIFO Write/read> field = 1 0 = TXFIFO is selected for both writes and reads through the SSP Data Register 1 = RXFIFO is selected for both writes and reads through the SSP Data Register

StrfW

Field STRF writer - Select FIFO For Efwr (Test Mode Bit) Only when the <Enable FIFO Write/read> field = 1 0 = TXFIFO is selected for both writes and reads through the SSP Data Register 1 = RXFIFO is selected for both writes and reads through the SSP Data Register

TftR

Field TFT reader - TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1.

TftW

Field TFT writer - TXFIFO Trigger Threshold This field sets the threshold level at which TXFIFO asserts interrupt. The level should be set to the preferred threshold value minus 1.

TsreR

Field TSRE reader - Transmit Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled

TsreW

Field TSRE writer - Transmit Service Request Enable 0 = DMA service request is disabled 1 = DMA service request is enabled

TxfifoWrEndianR

Field TXFIFO_WR_ENDIAN reader - apb_pwdata Write to Tx FIFO Endian 0x0 = txfifo_wdata[31:0] = apb_pwdata[31:0] 0x1 = fifo_wdata[31:0] = {apb_pwdata[15:0], apb_pwdata[31:16]} 0x2 = txfifo_wdata[31:0] = {apb_pwdata[7:0], apb_pwdata[15:8], apb_pwdata[23:16], apb_pwdata[31:24]} 0x3 = txfifo_wdata[31:0] = {apb_pwdata[23:16], apb_pwdata[31:24], apb_pwdata[7:0], apb_pwdata[15:8]}

TxfifoWrEndianW

Field TXFIFO_WR_ENDIAN writer - apb_pwdata Write to Tx FIFO Endian 0x0 = txfifo_wdata[31:0] = apb_pwdata[31:0] 0x1 = fifo_wdata[31:0] = {apb_pwdata[15:0], apb_pwdata[31:16]} 0x2 = txfifo_wdata[31:0] = {apb_pwdata[7:0], apb_pwdata[15:8], apb_pwdata[23:16], apb_pwdata[31:24]} 0x3 = txfifo_wdata[31:0] = {apb_pwdata[23:16], apb_pwdata[31:24], apb_pwdata[7:0], apb_pwdata[15:8]}

W

Register FIFO_CTRL writer