Module audio_i2s_sl_merge 

Structs

AudioI2sSlMergeSpec

You can read this register and get audio_i2s_sl_merge::R. You can reset, write, write_with_zero this register using audio_i2s_sl_merge::W. You can also modify this register. See API.

Type Aliases

R

Register AUDIO_I2S_SL_MERGE reader

RsvdR

Field RSVD reader -

RsvdW

Field RSVD writer -

SlaveTimingMergeR

Field SLAVE_TIMING_MERGE reader - when work as an I2S slave, and external I2S master TX/RX share an only BCLK/LRCK, we need set this bit high. 0: I2S slave use separated timing control port. TX_BCLK_IN/TX_LRCK_IN and RX_BCLK/RX_LRCK_IN are separated. 1: I2S slave use the same BCLK/LRCK, the TX_BCLK_IN/TX_LRCK also is used for RX controller.

SlaveTimingMergeW

Field SLAVE_TIMING_MERGE writer - when work as an I2S slave, and external I2S master TX/RX share an only BCLK/LRCK, we need set this bit high. 0: I2S slave use separated timing control port. TX_BCLK_IN/TX_LRCK_IN and RX_BCLK/RX_LRCK_IN are separated. 1: I2S slave use the same BCLK/LRCK, the TX_BCLK_IN/TX_LRCK also is used for RX controller.

W

Register AUDIO_I2S_SL_MERGE writer