sdmmc_driver/
timing.rs

1/// Represents the SD/MMC timing configuration.
2#[repr(u8)]
3#[derive(Clone, Copy, Debug, Eq, PartialEq)]
4pub enum Timing {
5    Legacy = 0,
6    MmcHs = 1,
7    SdHs = 2,
8    UhsSdr12 = 3,
9    UhsSdr25 = 4,
10    UhsSdr50 = 5,
11    UhsSdr104 = 6,
12    UhsDdr50 = 7,
13    MmcDdr52 = 8,
14    MmcHs200 = 9,
15    MmcHs400 = 10,
16    SdExp = 11,
17    SdExp1_2V = 12,
18    Uhs2SpeedA = 13,
19    Uhs2SpeedAHd = 14,
20    Uhs2SpeedB = 15,
21    Uhs2SpeedBHd = 16,
22}
23
24impl Timing {
25    /// Creates a new [Timing].
26    pub const fn new() -> Self {
27        Self::Legacy
28    }
29}
30
31impl Default for Timing {
32    fn default() -> Self {
33        Self::new()
34    }
35}
sdmmc_driver/timing.rs

sdmmc_driver/
timing.rs
