Expand description
A SystemVerilog (concrete) syntax tree for representing 1800-2023 syntax.
Each syntactic category is represented as a struct or enum with the same name as appears in Annex A, with additional types as needed for unnamed alternatives.
While the tree can be treated as a normal data structure, it can
also be iterated across (depth-first). Iterating produces Nodes,
which reference a specific data structure in the tree
fn is_always_comb_block<'a, 'b>(node: Node<'a, 'b>) -> bool {
matches!(node, Node::AlwaysConstruct(AlwaysConstruct(AlwaysKeyword::AlwaysComb(_), _)))
}
fn num_inferred_latches<'a>(source: &SourceText<'a>) -> i32 {
let mut count = 0;
for node in source.find(is_always_comb_block) {
for child_node in node.iter() {
if let Node::BlockingAssignment(_) = child_node {
count += 1;
}
}
}
count
}Compiler directives are not supported due to their arbitrary location/semantics in a syntax tree.
§Features
lossless: Allows for whitespace/comments to be preserved inMetadata
Re-exports§
pub use behavioral_statements::*;pub use declarations::*;pub use expressions::*;pub use general::*;pub use instantiations::*;pub use iter::*;pub use metadata::*;pub use primitive_instances::*;pub use source_text::*;pub use specify_section::*;pub use udp_declaration_and_instantiation::*;
Modules§
- behavioral_
statements - CST Nodes from 1800-2023 A.6
- declarations
- CST Nodes from 1800-2023 A.2
- expressions
- CST Nodes from 1800-2023 A.8
- general
- CST Nodes from 1800-2023 A.9
- instantiations
- CST Nodes from 1800-2023 A.4
- iter
- Iterating over a CST
- metadata
- Extra metadata attached to leaf nodes to encode a CST
- primitive_
instances - CST Nodes from 1800-2023 A.3
- source_
text - CST Nodes from 1800-2023 A.1
- specify_
section - CST Nodes from 1800-2023 A.7
- udp_
declaration_ and_ instantiation - CST Nodes from 1800-2023 A.5
Enums§
- Node
- A reference to a data structure in a SystemVerilog CST