1use core::fmt;
2use core::str::FromStr;
3
4use num_derive::FromPrimitive;
5
6#[derive(Debug, Clone, Copy, PartialEq, FromPrimitive)]
7#[repr(u8)]
8pub enum Opcode {
9 Lddw,
10 Ldxb,
11 Ldxh,
12 Ldxw,
13 Ldxdw,
14 Stb,
15 Sth,
16 Stw,
17 Stdw,
18 Stxb,
19 Stxh,
20 Stxw,
21 Stxdw,
22 Add32,
23 Add32Imm,
24 Add32Reg,
25 Sub32,
26 Sub32Imm,
27 Sub32Reg,
28 Mul32,
29 Mul32Imm,
30 Mul32Reg,
31 Div32,
32 Div32Imm,
33 Div32Reg,
34 Or32,
35 Or32Imm,
36 Or32Reg,
37 And32,
38 And32Imm,
39 And32Reg,
40 Lsh32,
41 Lsh32Imm,
42 Lsh32Reg,
43 Rsh32,
44 Rsh32Imm,
45 Rsh32Reg,
46 Mod32,
47 Mod32Imm,
48 Mod32Reg,
49 Xor32,
50 Xor32Imm,
51 Xor32Reg,
52 Mov32,
53 Mov32Imm,
54 Mov32Reg,
55 Arsh32,
56 Arsh32Imm,
57 Arsh32Reg,
58 Lmul32,
59 Lmul32Imm,
60 Lmul32Reg,
61 Udiv32,
62 Udiv32Imm,
63 Udiv32Reg,
64 Urem32,
65 Urem32Imm,
66 Urem32Reg,
67 Sdiv32,
68 Sdiv32Imm,
69 Sdiv32Reg,
70 Srem32,
71 Srem32Imm,
72 Srem32Reg,
73 Le,
74 Be,
75 Add64,
76 Add64Imm,
77 Add64Reg,
78 Sub64,
79 Sub64Imm,
80 Sub64Reg,
81 Mul64,
82 Mul64Imm,
83 Mul64Reg,
84 Div64,
85 Div64Imm,
86 Div64Reg,
87 Or64,
88 Or64Imm,
89 Or64Reg,
90 And64,
91 And64Imm,
92 And64Reg,
93 Lsh64,
94 Lsh64Imm,
95 Lsh64Reg,
96 Rsh64,
97 Rsh64Imm,
98 Rsh64Reg,
99 Mod64,
100 Mod64Imm,
101 Mod64Reg,
102 Xor64,
103 Xor64Imm,
104 Xor64Reg,
105 Mov64,
106 Mov64Imm,
107 Mov64Reg,
108 Arsh64,
109 Arsh64Imm,
110 Arsh64Reg,
111 Hor64Imm,
112 Lmul64,
113 Lmul64Imm,
114 Lmul64Reg,
115 Uhmul64,
116 Uhmul64Imm,
117 Uhmul64Reg,
118 Udiv64,
119 Udiv64Imm,
120 Udiv64Reg,
121 Urem64,
122 Urem64Imm,
123 Urem64Reg,
124 Shmul64,
125 Shmul64Imm,
126 Shmul64Reg,
127 Sdiv64,
128 Sdiv64Imm,
129 Sdiv64Reg,
130 Srem64,
131 Srem64Imm,
132 Srem64Reg,
133 Neg32,
134 Neg64,
135 Ja,
136 Jeq,
137 JeqImm,
138 JeqReg,
139 Jgt,
140 JgtImm,
141 JgtReg,
142 Jge,
143 JgeImm,
144 JgeReg,
145 Jlt,
146 JltImm,
147 JltReg,
148 Jle,
149 JleImm,
150 JleReg,
151 Jset,
152 JsetImm,
153 JsetReg,
154 Jne,
155 JneImm,
156 JneReg,
157 Jsgt,
158 JsgtImm,
159 JsgtReg,
160 Jsge,
161 JsgeImm,
162 JsgeReg,
163 Jslt,
164 JsltImm,
165 JsltReg,
166 Jsle,
167 JsleImm,
168 JsleReg,
169 Call,
170 Callx,
171 Exit,
172}
173
174impl FromStr for Opcode {
175 type Err = &'static str;
176
177 fn from_str(s: &str) -> Result<Self, Self::Err> {
178 match s.to_lowercase().as_str() {
179 "lddw" => Ok(Opcode::Lddw),
180 "ldxb" => Ok(Opcode::Ldxb),
181 "ldxh" => Ok(Opcode::Ldxh),
182 "ldxw" => Ok(Opcode::Ldxw),
183 "ldxdw" => Ok(Opcode::Ldxdw),
184 "stb" => Ok(Opcode::Stb),
185 "sth" => Ok(Opcode::Sth),
186 "stw" => Ok(Opcode::Stw),
187 "stdw" => Ok(Opcode::Stdw),
188 "stxb" => Ok(Opcode::Stxb),
189 "stxh" => Ok(Opcode::Stxh),
190 "stxw" => Ok(Opcode::Stxw),
191 "stxdw" => Ok(Opcode::Stxdw),
192 "add32" => Ok(Opcode::Add32),
193 "sub32" => Ok(Opcode::Sub32),
194 "mul32" => Ok(Opcode::Mul32),
195 "div32" => Ok(Opcode::Div32),
196 "or32" => Ok(Opcode::Or32),
197 "and32" => Ok(Opcode::And32),
198 "lsh32" => Ok(Opcode::Lsh32),
199 "rsh32" => Ok(Opcode::Rsh32),
200 "neg32" => Ok(Opcode::Neg32),
201 "mod32" => Ok(Opcode::Mod32),
202 "xor32" => Ok(Opcode::Xor32),
203 "mov32" => Ok(Opcode::Mov32),
204 "arsh32" => Ok(Opcode::Arsh32),
205 "lmul32" => Ok(Opcode::Lmul32),
206 "udiv32" => Ok(Opcode::Udiv32),
207 "urem32" => Ok(Opcode::Urem32),
208 "sdiv32" => Ok(Opcode::Sdiv32),
209 "srem32" => Ok(Opcode::Srem32),
210 "le" => Ok(Opcode::Le),
211 "be" => Ok(Opcode::Be),
212 "add64" => Ok(Opcode::Add64),
213 "sub64" => Ok(Opcode::Sub64),
214 "mul64" => Ok(Opcode::Mul64),
215 "div64" => Ok(Opcode::Div64),
216 "or64" => Ok(Opcode::Or64),
217 "and64" => Ok(Opcode::And64),
218 "lsh64" => Ok(Opcode::Lsh64),
219 "rsh64" => Ok(Opcode::Rsh64),
220 "neg64" => Ok(Opcode::Neg64),
221 "mod64" => Ok(Opcode::Mod64),
222 "xor64" => Ok(Opcode::Xor64),
223 "mov64" => Ok(Opcode::Mov64),
224 "arsh64" => Ok(Opcode::Arsh64),
225 "hor64" => Ok(Opcode::Hor64Imm),
226 "lmul64" => Ok(Opcode::Lmul64),
227 "uhmul64" => Ok(Opcode::Uhmul64),
228 "udiv64" => Ok(Opcode::Udiv64),
229 "urem64" => Ok(Opcode::Urem64),
230 "shmul64" => Ok(Opcode::Shmul64),
231 "sdiv64" => Ok(Opcode::Sdiv64),
232 "srem64" => Ok(Opcode::Srem64),
233 "ja" => Ok(Opcode::Ja),
234 "jeq" => Ok(Opcode::Jeq),
235 "jgt" => Ok(Opcode::Jgt),
236 "jge" => Ok(Opcode::Jge),
237 "jlt" => Ok(Opcode::Jlt),
238 "jle" => Ok(Opcode::Jle),
239 "jset" => Ok(Opcode::Jset),
240 "jne" => Ok(Opcode::Jne),
241 "jsgt" => Ok(Opcode::Jsgt),
242 "jsge" => Ok(Opcode::Jsge),
243 "jslt" => Ok(Opcode::Jslt),
244 "jsle" => Ok(Opcode::Jsle),
245 "call" => Ok(Opcode::Call),
246 "callx" => Ok(Opcode::Callx),
247 "exit" => Ok(Opcode::Exit),
248 _ => Err("Invalid opcode"),
249 }
250 }
251}
252
253impl fmt::Display for Opcode {
254 fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
255 write!(f, "{}", self.to_str())
256 }
257}
258
259impl Opcode {
260 pub fn from_u8(u: u8) -> Option<Self> {
261 match u {
262 0x18 => Some(Opcode::Lddw),
263 0x71 => Some(Opcode::Ldxb),
264 0x69 => Some(Opcode::Ldxh),
265 0x61 => Some(Opcode::Ldxw),
266 0x79 => Some(Opcode::Ldxdw),
267 0x72 => Some(Opcode::Stb),
268 0x6a => Some(Opcode::Sth),
269 0x62 => Some(Opcode::Stw),
270 0x7a => Some(Opcode::Stdw),
271 0x73 => Some(Opcode::Stxb),
272 0x6b => Some(Opcode::Stxh),
273 0x63 => Some(Opcode::Stxw),
274 0x7b => Some(Opcode::Stxdw),
275 0x04 => Some(Opcode::Add32Imm),
276 0x0c => Some(Opcode::Add32Reg),
277 0x14 => Some(Opcode::Sub32Imm),
278 0x1c => Some(Opcode::Sub32Reg),
279 0x24 => Some(Opcode::Mul32Imm),
280 0x2c => Some(Opcode::Mul32Reg),
281 0x34 => Some(Opcode::Div32Imm),
282 0x3c => Some(Opcode::Div32Reg),
283 0x44 => Some(Opcode::Or32Imm),
284 0x4c => Some(Opcode::Or32Reg),
285 0x54 => Some(Opcode::And32Imm),
286 0x5c => Some(Opcode::And32Reg),
287 0x64 => Some(Opcode::Lsh32Imm),
288 0x6c => Some(Opcode::Lsh32Reg),
289 0x74 => Some(Opcode::Rsh32Imm),
290 0x7c => Some(Opcode::Rsh32Reg),
291 0x94 => Some(Opcode::Mod32Imm),
292 0x9c => Some(Opcode::Mod32Reg),
293 0xa4 => Some(Opcode::Xor32Imm),
294 0xac => Some(Opcode::Xor32Reg),
295 0xb4 => Some(Opcode::Mov32Imm),
296 0xbc => Some(Opcode::Mov32Reg),
297 0xc4 => Some(Opcode::Arsh32Imm),
298 0xcc => Some(Opcode::Arsh32Reg),
299 0x86 => Some(Opcode::Lmul32Imm),
300 0x8e => Some(Opcode::Lmul32Reg),
301 0x46 => Some(Opcode::Udiv32Imm),
302 0x4e => Some(Opcode::Udiv32Reg),
303 0x66 => Some(Opcode::Urem32Imm),
304 0x6e => Some(Opcode::Urem32Reg),
305 0xc6 => Some(Opcode::Sdiv32Imm),
306 0xce => Some(Opcode::Sdiv32Reg),
307 0xe6 => Some(Opcode::Srem32Imm),
308 0xee => Some(Opcode::Srem32Reg),
309 0xd4 => Some(Opcode::Le),
310 0xdc => Some(Opcode::Be),
311 0x07 => Some(Opcode::Add64Imm),
312 0x0f => Some(Opcode::Add64Reg),
313 0x17 => Some(Opcode::Sub64Imm),
314 0x1f => Some(Opcode::Sub64Reg),
315 0x27 => Some(Opcode::Mul64Imm),
316 0x2f => Some(Opcode::Mul64Reg),
317 0x37 => Some(Opcode::Div64Imm),
318 0x3f => Some(Opcode::Div64Reg),
319 0x47 => Some(Opcode::Or64Imm),
320 0x4f => Some(Opcode::Or64Reg),
321 0x57 => Some(Opcode::And64Imm),
322 0x5f => Some(Opcode::And64Reg),
323 0x67 => Some(Opcode::Lsh64Imm),
324 0x6f => Some(Opcode::Lsh64Reg),
325 0x77 => Some(Opcode::Rsh64Imm),
326 0x7f => Some(Opcode::Rsh64Reg),
327 0x97 => Some(Opcode::Mod64Imm),
328 0x9f => Some(Opcode::Mod64Reg),
329 0xa7 => Some(Opcode::Xor64Imm),
330 0xaf => Some(Opcode::Xor64Reg),
331 0xb7 => Some(Opcode::Mov64Imm),
332 0xbf => Some(Opcode::Mov64Reg),
333 0xc7 => Some(Opcode::Arsh64Imm),
334 0xcf => Some(Opcode::Arsh64Reg),
335 0xf7 => Some(Opcode::Hor64Imm),
336 0x96 => Some(Opcode::Lmul64Imm),
337 0x9e => Some(Opcode::Lmul64Reg),
338 0x36 => Some(Opcode::Uhmul64Imm),
339 0x3e => Some(Opcode::Uhmul64Reg),
340 0x56 => Some(Opcode::Udiv64Imm),
341 0x5e => Some(Opcode::Udiv64Reg),
342 0x76 => Some(Opcode::Urem64Imm),
343 0x7e => Some(Opcode::Urem64Reg),
344 0xb6 => Some(Opcode::Shmul64Imm),
345 0xbe => Some(Opcode::Shmul64Reg),
346 0xd6 => Some(Opcode::Sdiv64Imm),
347 0xde => Some(Opcode::Sdiv64Reg),
348 0xf6 => Some(Opcode::Srem64Imm),
349 0xfe => Some(Opcode::Srem64Reg),
350 0x84 => Some(Opcode::Neg32),
351 0x87 => Some(Opcode::Neg64),
352 0x05 => Some(Opcode::Ja),
353 0x15 => Some(Opcode::JeqImm),
354 0x1d => Some(Opcode::JeqReg),
355 0x25 => Some(Opcode::JgtImm),
356 0x2d => Some(Opcode::JgtReg),
357 0x35 => Some(Opcode::JgeImm),
358 0x3d => Some(Opcode::JgeReg),
359 0xa5 => Some(Opcode::JltImm),
360 0xad => Some(Opcode::JltReg),
361 0xb5 => Some(Opcode::JleImm),
362 0xbd => Some(Opcode::JleReg),
363 0x45 => Some(Opcode::JsetImm),
364 0x4d => Some(Opcode::JsetReg),
365 0x55 => Some(Opcode::JneImm),
366 0x5d => Some(Opcode::JneReg),
367 0x65 => Some(Opcode::JsgtImm),
368 0x6d => Some(Opcode::JsgtReg),
369 0x75 => Some(Opcode::JsgeImm),
370 0x7d => Some(Opcode::JsgeReg),
371 0xc5 => Some(Opcode::JsltImm),
372 0xcd => Some(Opcode::JsltReg),
373 0xd5 => Some(Opcode::JsleImm),
374 0xdd => Some(Opcode::JsleReg),
375 0x85 => Some(Opcode::Call),
376 0x8d => Some(Opcode::Callx),
377 0x95 => Some(Opcode::Exit),
378 _ => None,
379 }
380 }
381
382 pub fn to_bytecode(&self) -> u8 {
383 match self {
384 Opcode::Lddw => 0x18,
385 Opcode::Ldxb => 0x71,
386 Opcode::Ldxh => 0x69,
387 Opcode::Ldxw => 0x61,
388 Opcode::Ldxdw => 0x79,
389 Opcode::Stb => 0x72,
390 Opcode::Sth => 0x6a,
391 Opcode::Stw => 0x62,
392 Opcode::Stdw => 0x7a,
393 Opcode::Stxb => 0x73,
394 Opcode::Stxh => 0x6b,
395 Opcode::Stxw => 0x63,
396 Opcode::Stxdw => 0x7b,
397 Opcode::Add32Imm => 0x04,
399 Opcode::Add32Reg => 0x0c,
400 Opcode::Sub32Imm => 0x14,
402 Opcode::Sub32Reg => 0x1c,
403 Opcode::Mul32Imm => 0x24,
405 Opcode::Mul32Reg => 0x2c,
406 Opcode::Div32Imm => 0x34,
408 Opcode::Div32Reg => 0x3c,
409 Opcode::Or32Imm => 0x44,
411 Opcode::Or32Reg => 0x4c,
412 Opcode::And32Imm => 0x54,
414 Opcode::And32Reg => 0x5c,
415 Opcode::Lsh32Imm => 0x64,
417 Opcode::Lsh32Reg => 0x6c,
418 Opcode::Rsh32Imm => 0x74,
420 Opcode::Rsh32Reg => 0x7c,
421 Opcode::Mod32Imm => 0x94,
423 Opcode::Mod32Reg => 0x9c,
424 Opcode::Xor32Imm => 0xa4,
426 Opcode::Xor32Reg => 0xac,
427 Opcode::Mov32Imm => 0xb4,
429 Opcode::Mov32Reg => 0xbc,
430 Opcode::Arsh32Imm => 0xc4,
432 Opcode::Arsh32Reg => 0xcc,
433 Opcode::Lmul32Imm => 0x86,
435 Opcode::Lmul32Reg => 0x8e,
436 Opcode::Udiv32Imm => 0x46,
438 Opcode::Udiv32Reg => 0x4e,
439 Opcode::Urem32Imm => 0x66,
441 Opcode::Urem32Reg => 0x6e,
442 Opcode::Sdiv32Imm => 0xc6,
444 Opcode::Sdiv32Reg => 0xce,
445 Opcode::Srem32Imm => 0xe6,
447 Opcode::Srem32Reg => 0xee,
448 Opcode::Le => 0xd4,
449 Opcode::Be => 0xdc,
450 Opcode::Add64Imm => 0x07,
452 Opcode::Add64Reg => 0x0f,
453 Opcode::Sub64Imm => 0x17,
455 Opcode::Sub64Reg => 0x1f,
456 Opcode::Mul64Imm => 0x27,
458 Opcode::Mul64Reg => 0x2f,
459 Opcode::Div64Imm => 0x37,
461 Opcode::Div64Reg => 0x3f,
462 Opcode::Or64Imm => 0x47,
464 Opcode::Or64Reg => 0x4f,
465 Opcode::And64Imm => 0x57,
467 Opcode::And64Reg => 0x5f,
468 Opcode::Lsh64Imm => 0x67,
470 Opcode::Lsh64Reg => 0x6f,
471 Opcode::Rsh64Imm => 0x77,
473 Opcode::Rsh64Reg => 0x7f,
474 Opcode::Mod64Imm => 0x97,
476 Opcode::Mod64Reg => 0x9f,
477 Opcode::Xor64Imm => 0xa7,
479 Opcode::Xor64Reg => 0xaf,
480 Opcode::Mov64Imm => 0xb7,
482 Opcode::Mov64Reg => 0xbf,
483 Opcode::Arsh64Imm => 0xc7,
485 Opcode::Arsh64Reg => 0xcf,
486 Opcode::Hor64Imm => 0xf7,
487 Opcode::Lmul64Imm => 0x96,
489 Opcode::Lmul64Reg => 0x9e,
490 Opcode::Uhmul64Imm => 0x36,
492 Opcode::Uhmul64Reg => 0x3e,
493 Opcode::Udiv64Imm => 0x56,
495 Opcode::Udiv64Reg => 0x5e,
496 Opcode::Urem64Imm => 0x76,
498 Opcode::Urem64Reg => 0x7e,
499 Opcode::Shmul64Imm => 0xb6,
501 Opcode::Shmul64Reg => 0xbe,
502 Opcode::Sdiv64Imm => 0xd6,
504 Opcode::Sdiv64Reg => 0xde,
505 Opcode::Srem64Imm => 0xf6,
507 Opcode::Srem64Reg => 0xfe,
508 Opcode::Neg32 => 0x84,
509 Opcode::Neg64 => 0x87,
510 Opcode::Ja => 0x05,
511 Opcode::JeqImm => 0x15,
513 Opcode::JeqReg => 0x1d,
514 Opcode::JgtImm => 0x25,
516 Opcode::JgtReg => 0x2d,
517 Opcode::JgeImm => 0x35,
519 Opcode::JgeReg => 0x3d,
520 Opcode::JltImm => 0xa5,
522 Opcode::JltReg => 0xad,
523 Opcode::JleImm => 0xb5,
525 Opcode::JleReg => 0xbd,
526 Opcode::JsetImm => 0x45,
528 Opcode::JsetReg => 0x4d,
529 Opcode::JneImm => 0x55,
531 Opcode::JneReg => 0x5d,
532 Opcode::JsgtImm => 0x65,
534 Opcode::JsgtReg => 0x6d,
535 Opcode::JsgeImm => 0x75,
537 Opcode::JsgeReg => 0x7d,
538 Opcode::JsltImm => 0xc5,
540 Opcode::JsltReg => 0xcd,
541 Opcode::JsleImm => 0xd5,
543 Opcode::JsleReg => 0xdd,
544 Opcode::Call => 0x85,
545 Opcode::Callx => 0x8d,
546 Opcode::Exit => 0x95,
547
548 _ => 0x00,
549 }
550 }
551
552 pub fn to_str(&self) -> &'static str {
553 match self {
554 Opcode::Lddw => "lddw",
555 Opcode::Ldxb => "ldxb",
556 Opcode::Ldxh => "ldxh",
557 Opcode::Ldxw => "ldxw",
558 Opcode::Ldxdw => "ldxdw",
559 Opcode::Stb => "stb",
560 Opcode::Sth => "sth",
561 Opcode::Stw => "stw",
562 Opcode::Stdw => "stdw",
563 Opcode::Stxb => "stxb",
564 Opcode::Stxh => "stxh",
565 Opcode::Stxw => "stxw",
566 Opcode::Stxdw => "stxdw",
567 Opcode::Add32 | Opcode::Add32Imm | Opcode::Add32Reg => "add32",
568 Opcode::Sub32 | Opcode::Sub32Imm | Opcode::Sub32Reg => "sub32",
569 Opcode::Mul32 | Opcode::Mul32Imm | Opcode::Mul32Reg => "mul32",
570 Opcode::Div32 | Opcode::Div32Imm | Opcode::Div32Reg => "div32",
571 Opcode::Or32 | Opcode::Or32Imm | Opcode::Or32Reg => "or32",
572 Opcode::And32 | Opcode::And32Imm | Opcode::And32Reg => "and32",
573 Opcode::Lsh32 | Opcode::Lsh32Imm | Opcode::Lsh32Reg => "lsh32",
574 Opcode::Rsh32 | Opcode::Rsh32Imm | Opcode::Rsh32Reg => "rsh32",
575 Opcode::Neg32 => "neg32",
576 Opcode::Mod32 | Opcode::Mod32Imm | Opcode::Mod32Reg => "mod32",
577 Opcode::Xor32 | Opcode::Xor32Imm | Opcode::Xor32Reg => "xor32",
578 Opcode::Mov32 | Opcode::Mov32Imm | Opcode::Mov32Reg => "mov32",
579 Opcode::Arsh32 | Opcode::Arsh32Imm | Opcode::Arsh32Reg => "arsh32",
580 Opcode::Lmul32 | Opcode::Lmul32Imm | Opcode::Lmul32Reg => "lmul32",
581 Opcode::Udiv32 | Opcode::Udiv32Imm | Opcode::Udiv32Reg => "udiv32",
582 Opcode::Urem32 | Opcode::Urem32Imm | Opcode::Urem32Reg => "urem32",
583 Opcode::Sdiv32 | Opcode::Sdiv32Imm | Opcode::Sdiv32Reg => "sdiv32",
584 Opcode::Srem32 | Opcode::Srem32Imm | Opcode::Srem32Reg => "srem32",
585 Opcode::Le => "le",
586 Opcode::Be => "be",
587 Opcode::Add64 | Opcode::Add64Imm | Opcode::Add64Reg => "add64",
588 Opcode::Sub64 | Opcode::Sub64Imm | Opcode::Sub64Reg => "sub64",
589 Opcode::Mul64 | Opcode::Mul64Imm | Opcode::Mul64Reg => "mul64",
590 Opcode::Div64 | Opcode::Div64Imm | Opcode::Div64Reg => "div64",
591 Opcode::Or64 | Opcode::Or64Imm | Opcode::Or64Reg => "or64",
592 Opcode::And64 | Opcode::And64Imm | Opcode::And64Reg => "and64",
593 Opcode::Lsh64 | Opcode::Lsh64Imm | Opcode::Lsh64Reg => "lsh64",
594 Opcode::Rsh64 | Opcode::Rsh64Imm | Opcode::Rsh64Reg => "rsh64",
595 Opcode::Neg64 => "neg64",
596 Opcode::Mod64 | Opcode::Mod64Imm | Opcode::Mod64Reg => "mod64",
597 Opcode::Xor64 | Opcode::Xor64Imm | Opcode::Xor64Reg => "xor64",
598 Opcode::Mov64 | Opcode::Mov64Imm | Opcode::Mov64Reg => "mov64",
599 Opcode::Arsh64 | Opcode::Arsh64Imm | Opcode::Arsh64Reg => "arsh64",
600 Opcode::Hor64Imm => "hor64",
601 Opcode::Lmul64 | Opcode::Lmul64Imm | Opcode::Lmul64Reg => "lmul64",
602 Opcode::Uhmul64 | Opcode::Uhmul64Imm | Opcode::Uhmul64Reg => "uhmul64",
603 Opcode::Udiv64 | Opcode::Udiv64Imm | Opcode::Udiv64Reg => "udiv64",
604 Opcode::Urem64 | Opcode::Urem64Imm | Opcode::Urem64Reg => "urem64",
605 Opcode::Shmul64 | Opcode::Shmul64Imm | Opcode::Shmul64Reg => "shmul64",
606 Opcode::Sdiv64 | Opcode::Sdiv64Imm | Opcode::Sdiv64Reg => "sdiv64",
607 Opcode::Srem64 | Opcode::Srem64Imm | Opcode::Srem64Reg => "srem64",
608 Opcode::Ja | Opcode::Jeq | Opcode::JeqImm | Opcode::JeqReg => "jeq",
609 Opcode::Jgt | Opcode::JgtImm | Opcode::JgtReg => "jgt",
610 Opcode::Jge | Opcode::JgeImm | Opcode::JgeReg => "jge",
611 Opcode::Jlt | Opcode::JltImm | Opcode::JltReg => "jlt",
612 Opcode::Jle | Opcode::JleImm | Opcode::JleReg => "jle",
613 Opcode::Jset | Opcode::JsetImm | Opcode::JsetReg => "jset",
614 Opcode::Jne | Opcode::JneImm | Opcode::JneReg => "jne",
615 Opcode::Jsgt | Opcode::JsgtImm | Opcode::JsgtReg => "jsgt",
616 Opcode::Jsge | Opcode::JsgeImm | Opcode::JsgeReg => "jsge",
617 Opcode::Jslt | Opcode::JsltImm | Opcode::JsltReg => "jslt",
618 Opcode::Jsle | Opcode::JsleImm | Opcode::JsleReg => "jsle",
619 Opcode::Call | Opcode::Callx => "call",
620 Opcode::Exit => "exit",
621 }
622 }
623}