sass_assembler/instructions/
mod.rs

1//! SASS instructions for NVIDIA GPUs.
2
3use serde::{Deserialize, Serialize};
4
5/// SASS register
6#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
7pub enum SassReg {
8    /// General purpose register
9    R(u8),
10    /// Uniform register
11    UR(u8),
12    /// Predicate register
13    PR(u8),
14}
15
16impl std::fmt::Display for SassReg {
17    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
18        match self {
19            SassReg::R(n) => write!(f, "R{}", n),
20            SassReg::UR(n) => write!(f, "UR{}", n),
21            SassReg::PR(n) => write!(f, "P{}", n),
22        }
23    }
24}
25
26/// SASS instruction set (Maxwell/Pascal/Ampere/Hopper base)
27#[derive(Debug, Clone, PartialEq, Serialize, Deserialize)]
28pub enum SassInstruction {
29    /// Floating-point add: FADD dst, src0, src1
30    FAdd { dst: SassReg, src0: SassReg, src1: SassReg },
31    /// Floating-point multiply: FMUL dst, src0, src1
32    FMul { dst: SassReg, src0: SassReg, src1: SassReg },
33    /// Tensor core multiply-accumulate: IMMA dst, src0, src1, src2
34    Imma { dst: SassReg, src0: SassReg, src1: SassReg, src2: SassReg },
35    /// Memory load: LDG.E dst, [addr]
36    Ldg { dst: SassReg, addr: SassReg },
37    /// Memory store: STG.E [addr], src
38    Stg { addr: SassReg, src: SassReg },
39    /// Control flow: EXIT
40    Exit,
41    /// Control flow: NOP
42    Nop,
43}
sass_assembler/instructions/mod.rs

sass_assembler/instructions/
mod.rs
