[][src]Type Definition saml10e15a::mclk::CPUDIV

type CPUDIV = Reg<u8, _CPUDIV>;

CPU Clock Division

This register you can read, reset, write, write_with_zero, modify. See API.

For information about avaliable fields see cpudiv module

Trait Implementations

impl Readable for CPUDIV[src]

read() method returns cpudiv::R reader structure

impl Writable for CPUDIV[src]

write(|w| ..) method takes cpudiv::W writer structure

impl ResetValue for CPUDIV[src]

Register CPUDIV reset()'s with value 0x01

type Type = u8

Register size