saml10d14a/rtc/mode0/
ctrlb.rs

1#[doc = "Reader of register CTRLB"]
2pub type R = crate::R<u16, super::CTRLB>;
3#[doc = "Writer for register CTRLB"]
4pub type W = crate::W<u16, super::CTRLB>;
5#[doc = "Register CTRLB `reset()`'s with value 0"]
6impl crate::ResetValue for super::CTRLB {
7    type Type = u16;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `GP0EN`"]
14pub type GP0EN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `GP0EN`"]
16pub struct GP0EN_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> GP0EN_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u16) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `DEBMAJ`"]
38pub type DEBMAJ_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `DEBMAJ`"]
40pub struct DEBMAJ_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> DEBMAJ_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u16) & 0x01) << 4);
58        self.w
59    }
60}
61#[doc = "Reader of field `DEBASYNC`"]
62pub type DEBASYNC_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `DEBASYNC`"]
64pub struct DEBASYNC_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> DEBASYNC_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u16) & 0x01) << 5);
82        self.w
83    }
84}
85#[doc = "Reader of field `RTCOUT`"]
86pub type RTCOUT_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `RTCOUT`"]
88pub struct RTCOUT_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> RTCOUT_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u16) & 0x01) << 6);
106        self.w
107    }
108}
109#[doc = "Reader of field `DMAEN`"]
110pub type DMAEN_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `DMAEN`"]
112pub struct DMAEN_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> DMAEN_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
130        self.w
131    }
132}
133#[doc = "Possible values of the field `DEBF`"]
134#[derive(Clone, Copy, Debug, PartialEq)]
135pub enum DEBF_A {
136    #[doc = "CLK_RTC_DEB = CLK_RTC/2"]
137    DIV2,
138    #[doc = "CLK_RTC_DEB = CLK_RTC/4"]
139    DIV4,
140    #[doc = "CLK_RTC_DEB = CLK_RTC/8"]
141    DIV8,
142    #[doc = "CLK_RTC_DEB = CLK_RTC/16"]
143    DIV16,
144    #[doc = "CLK_RTC_DEB = CLK_RTC/32"]
145    DIV32,
146    #[doc = "CLK_RTC_DEB = CLK_RTC/64"]
147    DIV64,
148    #[doc = "CLK_RTC_DEB = CLK_RTC/128"]
149    DIV128,
150    #[doc = "CLK_RTC_DEB = CLK_RTC/256"]
151    DIV256,
152}
153impl crate::ToBits<u8> for DEBF_A {
154    #[inline(always)]
155    fn _bits(&self) -> u8 {
156        match *self {
157            DEBF_A::DIV2 => 0,
158            DEBF_A::DIV4 => 1,
159            DEBF_A::DIV8 => 2,
160            DEBF_A::DIV16 => 3,
161            DEBF_A::DIV32 => 4,
162            DEBF_A::DIV64 => 5,
163            DEBF_A::DIV128 => 6,
164            DEBF_A::DIV256 => 7,
165        }
166    }
167}
168#[doc = "Reader of field `DEBF`"]
169pub type DEBF_R = crate::R<u8, DEBF_A>;
170impl DEBF_R {
171    #[doc = r"Get enumerated values variant"]
172    #[inline(always)]
173    pub fn variant(&self) -> DEBF_A {
174        match self.bits {
175            0 => DEBF_A::DIV2,
176            1 => DEBF_A::DIV4,
177            2 => DEBF_A::DIV8,
178            3 => DEBF_A::DIV16,
179            4 => DEBF_A::DIV32,
180            5 => DEBF_A::DIV64,
181            6 => DEBF_A::DIV128,
182            7 => DEBF_A::DIV256,
183            _ => unreachable!(),
184        }
185    }
186    #[doc = "Checks if the value of the field is `DIV2`"]
187    #[inline(always)]
188    pub fn is_div2(&self) -> bool {
189        *self == DEBF_A::DIV2
190    }
191    #[doc = "Checks if the value of the field is `DIV4`"]
192    #[inline(always)]
193    pub fn is_div4(&self) -> bool {
194        *self == DEBF_A::DIV4
195    }
196    #[doc = "Checks if the value of the field is `DIV8`"]
197    #[inline(always)]
198    pub fn is_div8(&self) -> bool {
199        *self == DEBF_A::DIV8
200    }
201    #[doc = "Checks if the value of the field is `DIV16`"]
202    #[inline(always)]
203    pub fn is_div16(&self) -> bool {
204        *self == DEBF_A::DIV16
205    }
206    #[doc = "Checks if the value of the field is `DIV32`"]
207    #[inline(always)]
208    pub fn is_div32(&self) -> bool {
209        *self == DEBF_A::DIV32
210    }
211    #[doc = "Checks if the value of the field is `DIV64`"]
212    #[inline(always)]
213    pub fn is_div64(&self) -> bool {
214        *self == DEBF_A::DIV64
215    }
216    #[doc = "Checks if the value of the field is `DIV128`"]
217    #[inline(always)]
218    pub fn is_div128(&self) -> bool {
219        *self == DEBF_A::DIV128
220    }
221    #[doc = "Checks if the value of the field is `DIV256`"]
222    #[inline(always)]
223    pub fn is_div256(&self) -> bool {
224        *self == DEBF_A::DIV256
225    }
226}
227#[doc = "Write proxy for field `DEBF`"]
228pub struct DEBF_W<'a> {
229    w: &'a mut W,
230}
231impl<'a> DEBF_W<'a> {
232    #[doc = r"Writes `variant` to the field"]
233    #[inline(always)]
234    pub fn variant(self, variant: DEBF_A) -> &'a mut W {
235        use crate::ToBits;
236        {
237            self.bits(variant._bits())
238        }
239    }
240    #[doc = "CLK_RTC_DEB = CLK_RTC/2"]
241    #[inline(always)]
242    pub fn div2(self) -> &'a mut W {
243        self.variant(DEBF_A::DIV2)
244    }
245    #[doc = "CLK_RTC_DEB = CLK_RTC/4"]
246    #[inline(always)]
247    pub fn div4(self) -> &'a mut W {
248        self.variant(DEBF_A::DIV4)
249    }
250    #[doc = "CLK_RTC_DEB = CLK_RTC/8"]
251    #[inline(always)]
252    pub fn div8(self) -> &'a mut W {
253        self.variant(DEBF_A::DIV8)
254    }
255    #[doc = "CLK_RTC_DEB = CLK_RTC/16"]
256    #[inline(always)]
257    pub fn div16(self) -> &'a mut W {
258        self.variant(DEBF_A::DIV16)
259    }
260    #[doc = "CLK_RTC_DEB = CLK_RTC/32"]
261    #[inline(always)]
262    pub fn div32(self) -> &'a mut W {
263        self.variant(DEBF_A::DIV32)
264    }
265    #[doc = "CLK_RTC_DEB = CLK_RTC/64"]
266    #[inline(always)]
267    pub fn div64(self) -> &'a mut W {
268        self.variant(DEBF_A::DIV64)
269    }
270    #[doc = "CLK_RTC_DEB = CLK_RTC/128"]
271    #[inline(always)]
272    pub fn div128(self) -> &'a mut W {
273        self.variant(DEBF_A::DIV128)
274    }
275    #[doc = "CLK_RTC_DEB = CLK_RTC/256"]
276    #[inline(always)]
277    pub fn div256(self) -> &'a mut W {
278        self.variant(DEBF_A::DIV256)
279    }
280    #[doc = r"Writes raw bits to the field"]
281    #[inline(always)]
282    pub fn bits(self, value: u8) -> &'a mut W {
283        self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u16) & 0x07) << 8);
284        self.w
285    }
286}
287#[doc = "Possible values of the field `ACTF`"]
288#[derive(Clone, Copy, Debug, PartialEq)]
289pub enum ACTF_A {
290    #[doc = "CLK_RTC_OUT = CLK_RTC/2"]
291    DIV2,
292    #[doc = "CLK_RTC_OUT = CLK_RTC/4"]
293    DIV4,
294    #[doc = "CLK_RTC_OUT = CLK_RTC/8"]
295    DIV8,
296    #[doc = "CLK_RTC_OUT = CLK_RTC/16"]
297    DIV16,
298    #[doc = "CLK_RTC_OUT = CLK_RTC/32"]
299    DIV32,
300    #[doc = "CLK_RTC_OUT = CLK_RTC/64"]
301    DIV64,
302    #[doc = "CLK_RTC_OUT = CLK_RTC/128"]
303    DIV128,
304    #[doc = "CLK_RTC_OUT = CLK_RTC/256"]
305    DIV256,
306}
307impl crate::ToBits<u8> for ACTF_A {
308    #[inline(always)]
309    fn _bits(&self) -> u8 {
310        match *self {
311            ACTF_A::DIV2 => 0,
312            ACTF_A::DIV4 => 1,
313            ACTF_A::DIV8 => 2,
314            ACTF_A::DIV16 => 3,
315            ACTF_A::DIV32 => 4,
316            ACTF_A::DIV64 => 5,
317            ACTF_A::DIV128 => 6,
318            ACTF_A::DIV256 => 7,
319        }
320    }
321}
322#[doc = "Reader of field `ACTF`"]
323pub type ACTF_R = crate::R<u8, ACTF_A>;
324impl ACTF_R {
325    #[doc = r"Get enumerated values variant"]
326    #[inline(always)]
327    pub fn variant(&self) -> ACTF_A {
328        match self.bits {
329            0 => ACTF_A::DIV2,
330            1 => ACTF_A::DIV4,
331            2 => ACTF_A::DIV8,
332            3 => ACTF_A::DIV16,
333            4 => ACTF_A::DIV32,
334            5 => ACTF_A::DIV64,
335            6 => ACTF_A::DIV128,
336            7 => ACTF_A::DIV256,
337            _ => unreachable!(),
338        }
339    }
340    #[doc = "Checks if the value of the field is `DIV2`"]
341    #[inline(always)]
342    pub fn is_div2(&self) -> bool {
343        *self == ACTF_A::DIV2
344    }
345    #[doc = "Checks if the value of the field is `DIV4`"]
346    #[inline(always)]
347    pub fn is_div4(&self) -> bool {
348        *self == ACTF_A::DIV4
349    }
350    #[doc = "Checks if the value of the field is `DIV8`"]
351    #[inline(always)]
352    pub fn is_div8(&self) -> bool {
353        *self == ACTF_A::DIV8
354    }
355    #[doc = "Checks if the value of the field is `DIV16`"]
356    #[inline(always)]
357    pub fn is_div16(&self) -> bool {
358        *self == ACTF_A::DIV16
359    }
360    #[doc = "Checks if the value of the field is `DIV32`"]
361    #[inline(always)]
362    pub fn is_div32(&self) -> bool {
363        *self == ACTF_A::DIV32
364    }
365    #[doc = "Checks if the value of the field is `DIV64`"]
366    #[inline(always)]
367    pub fn is_div64(&self) -> bool {
368        *self == ACTF_A::DIV64
369    }
370    #[doc = "Checks if the value of the field is `DIV128`"]
371    #[inline(always)]
372    pub fn is_div128(&self) -> bool {
373        *self == ACTF_A::DIV128
374    }
375    #[doc = "Checks if the value of the field is `DIV256`"]
376    #[inline(always)]
377    pub fn is_div256(&self) -> bool {
378        *self == ACTF_A::DIV256
379    }
380}
381#[doc = "Write proxy for field `ACTF`"]
382pub struct ACTF_W<'a> {
383    w: &'a mut W,
384}
385impl<'a> ACTF_W<'a> {
386    #[doc = r"Writes `variant` to the field"]
387    #[inline(always)]
388    pub fn variant(self, variant: ACTF_A) -> &'a mut W {
389        use crate::ToBits;
390        {
391            self.bits(variant._bits())
392        }
393    }
394    #[doc = "CLK_RTC_OUT = CLK_RTC/2"]
395    #[inline(always)]
396    pub fn div2(self) -> &'a mut W {
397        self.variant(ACTF_A::DIV2)
398    }
399    #[doc = "CLK_RTC_OUT = CLK_RTC/4"]
400    #[inline(always)]
401    pub fn div4(self) -> &'a mut W {
402        self.variant(ACTF_A::DIV4)
403    }
404    #[doc = "CLK_RTC_OUT = CLK_RTC/8"]
405    #[inline(always)]
406    pub fn div8(self) -> &'a mut W {
407        self.variant(ACTF_A::DIV8)
408    }
409    #[doc = "CLK_RTC_OUT = CLK_RTC/16"]
410    #[inline(always)]
411    pub fn div16(self) -> &'a mut W {
412        self.variant(ACTF_A::DIV16)
413    }
414    #[doc = "CLK_RTC_OUT = CLK_RTC/32"]
415    #[inline(always)]
416    pub fn div32(self) -> &'a mut W {
417        self.variant(ACTF_A::DIV32)
418    }
419    #[doc = "CLK_RTC_OUT = CLK_RTC/64"]
420    #[inline(always)]
421    pub fn div64(self) -> &'a mut W {
422        self.variant(ACTF_A::DIV64)
423    }
424    #[doc = "CLK_RTC_OUT = CLK_RTC/128"]
425    #[inline(always)]
426    pub fn div128(self) -> &'a mut W {
427        self.variant(ACTF_A::DIV128)
428    }
429    #[doc = "CLK_RTC_OUT = CLK_RTC/256"]
430    #[inline(always)]
431    pub fn div256(self) -> &'a mut W {
432        self.variant(ACTF_A::DIV256)
433    }
434    #[doc = r"Writes raw bits to the field"]
435    #[inline(always)]
436    pub fn bits(self, value: u8) -> &'a mut W {
437        self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u16) & 0x07) << 12);
438        self.w
439    }
440}
441#[doc = "Reader of field `SEPTO`"]
442pub type SEPTO_R = crate::R<bool, bool>;
443#[doc = "Write proxy for field `SEPTO`"]
444pub struct SEPTO_W<'a> {
445    w: &'a mut W,
446}
447impl<'a> SEPTO_W<'a> {
448    #[doc = r"Sets the field bit"]
449    #[inline(always)]
450    pub fn set_bit(self) -> &'a mut W {
451        self.bit(true)
452    }
453    #[doc = r"Clears the field bit"]
454    #[inline(always)]
455    pub fn clear_bit(self) -> &'a mut W {
456        self.bit(false)
457    }
458    #[doc = r"Writes raw bits to the field"]
459    #[inline(always)]
460    pub fn bit(self, value: bool) -> &'a mut W {
461        self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
462        self.w
463    }
464}
465impl R {
466    #[doc = "Bit 0 - General Purpose 0 Enable"]
467    #[inline(always)]
468    pub fn gp0en(&self) -> GP0EN_R {
469        GP0EN_R::new((self.bits & 0x01) != 0)
470    }
471    #[doc = "Bit 4 - Debouncer Majority Enable"]
472    #[inline(always)]
473    pub fn debmaj(&self) -> DEBMAJ_R {
474        DEBMAJ_R::new(((self.bits >> 4) & 0x01) != 0)
475    }
476    #[doc = "Bit 5 - Debouncer Asynchronous Enable"]
477    #[inline(always)]
478    pub fn debasync(&self) -> DEBASYNC_R {
479        DEBASYNC_R::new(((self.bits >> 5) & 0x01) != 0)
480    }
481    #[doc = "Bit 6 - RTC Output Enable"]
482    #[inline(always)]
483    pub fn rtcout(&self) -> RTCOUT_R {
484        RTCOUT_R::new(((self.bits >> 6) & 0x01) != 0)
485    }
486    #[doc = "Bit 7 - DMA Enable"]
487    #[inline(always)]
488    pub fn dmaen(&self) -> DMAEN_R {
489        DMAEN_R::new(((self.bits >> 7) & 0x01) != 0)
490    }
491    #[doc = "Bits 8:10 - Debounce Frequency"]
492    #[inline(always)]
493    pub fn debf(&self) -> DEBF_R {
494        DEBF_R::new(((self.bits >> 8) & 0x07) as u8)
495    }
496    #[doc = "Bits 12:14 - Active Layer Frequency"]
497    #[inline(always)]
498    pub fn actf(&self) -> ACTF_R {
499        ACTF_R::new(((self.bits >> 12) & 0x07) as u8)
500    }
501    #[doc = "Bit 15 - Separate Tamper Outputs"]
502    #[inline(always)]
503    pub fn septo(&self) -> SEPTO_R {
504        SEPTO_R::new(((self.bits >> 15) & 0x01) != 0)
505    }
506}
507impl W {
508    #[doc = "Bit 0 - General Purpose 0 Enable"]
509    #[inline(always)]
510    pub fn gp0en(&mut self) -> GP0EN_W {
511        GP0EN_W { w: self }
512    }
513    #[doc = "Bit 4 - Debouncer Majority Enable"]
514    #[inline(always)]
515    pub fn debmaj(&mut self) -> DEBMAJ_W {
516        DEBMAJ_W { w: self }
517    }
518    #[doc = "Bit 5 - Debouncer Asynchronous Enable"]
519    #[inline(always)]
520    pub fn debasync(&mut self) -> DEBASYNC_W {
521        DEBASYNC_W { w: self }
522    }
523    #[doc = "Bit 6 - RTC Output Enable"]
524    #[inline(always)]
525    pub fn rtcout(&mut self) -> RTCOUT_W {
526        RTCOUT_W { w: self }
527    }
528    #[doc = "Bit 7 - DMA Enable"]
529    #[inline(always)]
530    pub fn dmaen(&mut self) -> DMAEN_W {
531        DMAEN_W { w: self }
532    }
533    #[doc = "Bits 8:10 - Debounce Frequency"]
534    #[inline(always)]
535    pub fn debf(&mut self) -> DEBF_W {
536        DEBF_W { w: self }
537    }
538    #[doc = "Bits 12:14 - Active Layer Frequency"]
539    #[inline(always)]
540    pub fn actf(&mut self) -> ACTF_W {
541        ACTF_W { w: self }
542    }
543    #[doc = "Bit 15 - Separate Tamper Outputs"]
544    #[inline(always)]
545    pub fn septo(&mut self) -> SEPTO_W {
546        SEPTO_W { w: self }
547    }
548}
saml10d14a/rtc/mode0/ctrlb.rs

saml10d14a/rtc/mode0/
ctrlb.rs
