Crate safety_net 

safety-net

An experimental library for representing circuit netlists for EDA tool development. Take a look at some examples and the documentation.

The most important API is the Netlist struct.

Simple Example

use safety_net::netlist::{Gate, Netlist};

fn and_gate() -> Gate {
    Gate::new_logical("AND".into(), vec!["A".into(), "B".into()], "Y".into())
}

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an AND gate
    let instance = netlist
        .insert_gate(and_gate(), "inst_0".into(), &[a, b])
        .unwrap();

    // Make this AND gate an output
    instance.expose_with_name("y".into());

    // Print the netlist
    println!("{netlist}");
}

Modules

attribute

Attributes and parameters for nets and node (gates) in the netlist.

circuit

Types for the constructs found within a digital circuit.

error

Error types.

graph

Graph utils for the graph module.

logic

Four-state logic

netlist

API for a netlist data structure.

Macros

assert_verilog_eq

Compare Verilog as strings up to indentation.

filter_nodes

Filter invariants of Instantiable in a netlist. Use it like you would matches!. Example: filter_nodes!(netlist, Gate::AND(_));

format_id

Functions like the format! macro, but returns an Identifier